MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 327

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-39
8.4.1.34
The memory data path read capture high register, shown in
data path during error capture.
Table 8-40
Freescale Semiconductor
16–21
24–31
0–14
0–31
Bits
Bits
15
22
23
Offset 0xE20
Reset
W
R
APIEN Address parity error injection enable. This bit is cleared by hardware after a single address parity error has
ECHD Error capture high data path. Captures the high word of the data path when errors are detected.
Name
Name
EEIM ECC error injection mask. Setting a mask bit causes the corresponding ECC bit to be inverted on memory
EIEN
EMB
—
—
0
describes the ERR_INJECT fields.
describes the CAPTURE_DATA_HI fields.
Figure 8-35. Memory Data Path Read Capture High Register (CAPTURE_DATA_HI)
Memory Data Path Read Capture High (CAPTURE_DATA_HI)
Reserved
been injected.
0 Address parity error injection disabled.
1 Address parity error injection enabled.
Reserved
ECC mirror byte
0 Mirror byte functionality disabled.
1 Mirror the most significant data path byte onto the ECC byte.
Error injection enable
0 Error injection disabled.
1 Error injection enabled. This applies to the data mask bits, the ECC mask bits, and the ECC mirror bit. Note
bus writes.
that error injection should not be enabled until the memory controller has been enabled through
DDR_SDRAM_CFG[MEM_EN].
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-40. CAPTURE_DATA_HI Field Descriptions
Table 8-39. ERR_INJECT Field Descriptions
All zeros
ECHD
Description
Description
Figure
8-35, stores the high word of the read
Access: Read/Write
DDR Memory Controller
31
8-53