MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 112

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Part IV, “Global Functions and Debug,” defines other global blocks of the MPC8536E. The following
chapters are included:
This reference manual also contains the following appendices:
It also contains a glossary and an index.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the architecture.
General Information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth Floor,
San Francisco, CA, provides useful information about the PowerPC architecture and computer architecture
in general:
Related Documentation
Freescale documentation is available from the sources listed on the back cover of this manual; the
document order numbers are included in parentheses for ease in ordering:
cxii
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Chapter 23, “Global Utilities,”
management, I/O device enabling, power-on-reset (POR) configuration monitoring,
general-purpose I/O signal use, and multiplexing for the interrupt and local bus chip select signals.
Chapter 24, “Device Performance Monitor,”
MPC8536E. Note that the MPC8536E performance monitor is similar to but separate from the
performance monitor implemented on the e500v2 core.
Chapter 25, “Debug Features and Watchpoint Facility,”
watchpoint monitor of the MPC8536E.
Appendix A, “Complete List of Configuration, Control, and Status
memory-mapped registers by block.
Appendix B, “Revision
document.
Appendix C,
The PowerPC Architecture: A Specification for a New Family of RISC Processors, Second Edition,
by International Business Machines, Inc.
Computer Architecture: A Quantitative Approach, Third Edition, by John L. Hennessy and David
A. Patterson
Computer Organization and Design: The Hardware/Software Interface, Second Edition, by David
A. Patterson and John L. Hennessy
EREF: A Reference for Freescale Book E and the e500 Core (EREF)—This book provides a
higher-level view of the programming model as it is defined by Book E, the Freescale Book E
implementation standards, and the e500 microprocessor.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
“MPC8535E,” details differences between the MPC8536E and MPC8535E devices.
History,” contains a list of major differences since the last revision of the
defines the global utilities of the MPC8536E. These include power
describes the performance monitor of the
describes the debug features and
Registers,” lists all
Freescale Semiconductor