MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1692

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

F–I
External writes, see L2 cache/SRAM, stashing
F
Fetch register, 10-44
FIFO RAM controller, 21-41
FSTNs
G
General Purpose I/O module (GPIO), see GPIO
Global utilities
Index-6
POR (LAD[0:31]) status, 4-24, 23-13
host controller operational model, 21-89
software operational model, 21-91
clock out
DDR controller
DMA signal multiplex control register (PMUXCR), 23-14
features, 23-1
functional description, 23-47
interrupt and local bus signal multiplexing, 23-1, 23-14
LBC voltage select, 23-31
machine check summary
memory map/register definition, 23-3
overview, 23-1
POR configuration
power management
processor version register (PVR), 23-29
register descriptions, 23-5
reset
signals summary, 23-2
CLK_OUT signal, 23-3, 23-33
clock out control register (CLKOCR), 23-33
overview, 23-1
clock disable, 23-32, 23-33
sources of mcp (MCPSUMR), 23-26
boot mode status register (PORBMSR), 23-6
debug mode status register (PORDBGMSR), 23-12
device status register (PORDEVSR), 23-9
I/O impedance status register (PORIMPSCR), 23-8
LAD[0:31] external system configuration (GPPORCR),
PLL status register (PORPLLSR), 23-5
see also Power-on reset (POR)
block disable (DEVDISR), 23-16
device mode control and status register
features, 23-1
functional description, 23-47
by acronym, see Register Index
HRESET_REQ control, 23-30
RapidIO and PCI Express reset requests (RSTRSCR),
4-24, 23-13
(POWMGTCSR), 23-19, 23-21
23-28
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
GPCM (LBC general-purpose chip-select machine), 13-48
GPIO
H
Hash function, see eTSEC, hash function
HRESET (hard reset) signal, 4-2, 4-8
HRESET_REQ (hard reset request) signal, 4-2, 11-18, 11-19
I
I/O impedance
I/O space
I
2
C interface
system version register (SVR), 23-30
see also Local bus controller (LBC)
block diagram, 22-1
features, 22-1
memory map/register definition, 22-2
overview, 22-1
registers, 22-2–22-5
signals, 22-2
LBC and PCI/PCI-X signals
PCI/PCI-X interface (POR), 4-22
PCI/PCI-X addressing, 16-48
arbitration
block diagram, 11-1
boot sequencer
boot sequencer mode, 11-2, 11-17–11-20
calling address match condition, 11-6
clock control, 11-16
data transfer, 11-13
error handling
features, 11-2
frequency divider
functional description, 11-11
handshaking, 11-16
implementation details, 11-13
see also Signals, global utilities
control and status register (global utilities), 23-8
arbitration control, 11-15
loss of arbitration—forcing of slave mode, 11-24
procedure for arbitration, 11-15
POR configuration, 4-18
error condition behavior, 11-19
clock stretching, 11-17
clock synchronization, 11-16
input synchronization and digital filter, 11-16
master mode, 11-16
slave mode, 11-16
boot sequencer mode, 11-19
frequency divider register (I2CFDR), 11-6
address compare, 11-15
Freescale Semiconductor
Index