MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 185

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
See
on the default boot ROM values. Also, see
for information on translation of the boot page.
4.4.3.7
The host/agent reset configuration inputs, shown in
or as an agent of a master on another interface. In host mode, the device is immediately enabled to master
transactions to the PCI interface. If the device is an agent on the PCI or PCI Express interfaces, then the
device is disabled from mastering transactions on that interface until the external host enables it to do so.
The external host does this by setting the control registers of the MPC8536E’s interfaces appropriately.
See details in the PCI and PCI Express, programming models described in
Interface,”
Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
Freescale Semiconductor
Functional Signals Reset Configuration Name
TSEC1_TXD[7:4]
Section 2.1, “Local Memory Map Overview and Example,”
Default (1111)
and
Host/Agent Configuration
Chapter 17, “PCI Express Interface Controller,”
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
cfg_rom_loc[0:3]
Table 4-14. Boot ROM Location
Section 4.3.1.3.1, “Boot Page Translation Register (BPTR),”
(Binary)
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table
PCI
PCI Express 1
PCI Express 2
PCI Express 3
DDR controller
Reserved
On-chip boot ROM eSPI configuration
On-chip boot ROM eSDHC configuration
Local bus FCM—8-bit NAND Flash small page ECC enabled
Local bus FCM—8-bit NAND Flash small page ECC disabled
Local bus FCM—8-bit NAND Flash large page ECC enabled
Local bus FCM—8-bit NAND Flash large page ECC disabled
Reserved
Local bus GPCM—8-bit ROM
Local bus GPCM—16-bit ROM
Local bus GPCM—32-bit ROM (default)
4-15, configure the MPC8536E to act as a host
Section 23.4.1.2, “POR Boot Mode Status
Section 23.4.1.2, “POR Boot Mode Status
respectively.
for an example memory map that relies
Meaning
Chapter 16, “PCI Bus
Reset, Clocking, and Initialization
4-15