MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1407

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

As noted above, the client request includes a pointer to the base of the buffer and offsets into the buffer to
annotate which buffer sections are to be used on each bus transaction that occurs on this endpoint. System
software must initialize each transaction description in an iTD to ensure it uses the correct portion of the
client buffer. For example, for each transaction description, the PG field is set to index the correct physical
buffer page pointer and the Transaction Offset field is set relative to the correct buffer pointer page (for
example, the same one referenced by the PG field). When the host controller executes a transaction it
selects a transaction description record based on FRINDEX[2–0]. It then uses the current Page Buffer
Pointer (as selected by the PG field) and concatenates to the transaction offset field. The result is a starting
buffer address for the transaction. As the host controller moves data for the transaction, it must watch for
a page wrap condition and properly advance to the next available Page Buffer Pointer. System software
must not use the Page 6 buffer pointer in a transaction description where the length of the transfer will wrap
a page boundary. Doing so yields undefined behavior. The host controller hardware is not required to alias
the page selector to page zero. USB 2.0 isochronous endpoints can specify a period greater than one.
Software can achieve the appropriate scheduling by linking iTDs into the appropriate frames (relative to
the frame list) and by setting appropriate transaction description elements active bits to a one.
21.6.8.2.1
The Isochronous Scheduling Threshold field in the HCCPARAMS capability register is an indicator to
system software as to how the host controller pre-fetches and effectively caches schedule data structures.
It is used by system software when adding isochronous work items to the periodic schedule. The value of
this field indicates to system software the minimum distance it can update isochronous data (relative to the
current location of the host controller execution in the periodic list) and still have the host controller
process them.
Freescale Semiconductor
Frame List
Frame i+1
Frame i+2
Frame i+n
Frame i
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Periodic Scheduling Threshold
Figure 21-47. Example Association of iTDs to Client Request Buffer
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
iTD
iTD
iTD
N
0
1
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Client Buffer
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Universal Serial Bus Interfaces
Transaction
Information
Request
Client
USB
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