MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1418

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.6.12 Split Transactions
USB 2.0 defines extensions to the bus protocol for managing USB 1.x data streams through USB 2.0 hubs.
This section describes how the host controller uses the interface data structures to manage data streams
with full- and low-speed devices, connected below a USB 2.0 hub, utilizing the split transaction protocol.
Refer to the USB 2.0 Specification for the complete definition of the split transaction protocol. Full- and
low-speed devices are enumerated identically as high-speed devices, but the transactions to the full- and
low-speed endpoints use the split-transaction protocol on the high-speed bus. The split transaction protocol
is an encapsulation of (or wrapper around) the full- or low-speed transaction. The high-speed wrapper
portion of the protocol is addressed to the USB 2.0 hub and transaction translator below which the full- or
low-speed device is attached.
EHCI uses dedicated data structures for managing full-speed isochronous data streams. Control, Bulk and
Interrupt are managed using the queuing data structures. The interface data structures need to be
programmed with the device address and the transaction translator number of the USB 2.0 hub operating
as the low-/full-speed host controller for this link. The following sections describe the details of how the
host controller processes and manages the split transaction protocol.
21.6.12.1 Split Transactions for Asynchronous Transfers
A queue head in the asynchronous schedule with an EPS field indicating a full-or low-speed device
indicates to the host controller that it must use split transactions to stream data for this queue head. All
full-speed bulk and full-, low-speed control are managed via queue heads in the asynchronous schedule.
Software must initialize the queue head with the appropriate device address and port number for the
transaction translator that is serving as the full-/low-speed host controller for the links connecting the
endpoint. Software must also initialize the split transaction state bit (SplitXState) to Do-Start-Split.
Finally, if the endpoint is a control endpoint, then system software must set the Control Transfer Type (C)
bit in the queue head to a one. If this is not a control transfer type endpoint, the C bit must be initialized
by software to be a zero. This information is used by the host controller to properly set the Endpoint Type
(ET) field in the split transaction bus token. When the C bit is a zero, the split transaction token's ET field
is set to indicate a bulk endpoint. When the C bit is a one, the split transaction token's ET field is set to
indicate a control endpoint. Refer to Chapter 8 of USB Specification, Revision 2.0 for details.
21-84
Error Count
Decrement
Figure 21-51. Host Controller Asynchronous Schedule Split-Transaction State Machine
Endpoint Halt
(CERR)
CERR goes
to Zero
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
XactErr
Endpoint Active
NaK
Start-
Split
Do
!XactErr
!NYET
.and.
.and.
!Stall
AcK
Complete-
Split
Do
Nyet
PidCode .eq. SETUP
XactErr
Endpoint Halt
Decrement Error Count
.and.
NaK
Set XactErr Bit and
Stall
(CERR)
Do Immediate Retry
of Complete-Split
Error Count
Decrement
Freescale Semiconductor
CERR goes
(CERR)
to Zero
and