MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 123

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.3
The following sections describe the major functional units of the MPC8536E.
1.3.1
The MPC8536E contains a high-performance 32-bit Book E-enhanced e500v2 core that implements the
PowerPC architecture.
In addition to 36-bit physical addressing, this version of the e500 core includes:
The MPC8536E contains a 512-Kbyte L2 cache/SRAM, as follows:
1.3.2
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be
routed or dispatched to target modules on the device.
Freescale Semiconductor
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Programmable interrupt controller (PIC)
Enhanced serial peripheral interface (eSPI)
Enhanced secure digital host controller (eSDHC)
Four-channel DMA controller
Two I
DUART
Enhanced local bus controller (eLBC)
16 general-purpose I/O signals (independently configurable)
Package pinout for low-cost PCB
Double-precision floating-point APU with an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit general-purpose registers.
Embedded vector and scalar single-precision floating-point APUs with an instruction set for
single-precision (32-bit) floating-point instructions.
Eight-way set-associative cache organization with 32-byte cache lines.
Per-way allocation of cache region to a given processor.
Flexible configuration (one, two, four, or eight ways can be configured as SRAM).
External masters can force data to be allocated into the cache through programmed memory ranges
or special transaction types (stashing).
SRAM:
— I/O devices access SRAM regions by marking transactions as snoopable (global).
— Regions can reside at any aligned location in the memory map.
— Byte-accessible ECC uses read-modify-write accesses for smaller-than-cache-line accesses.
MPC8536E Architecture Overview
e500 Core and Memory Unit
e500 Coherency Module (ECM) and Address Map
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C controllers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Overview
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