MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1225

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSB0
18.3.1.6
The 32-bit read-only eSPI receive data register (SPIRF) is used to hold characters read from the receive
FIFO. Each time SPIE[RNE] is set, the core can read the SPIRF register.
For character lengths of 4 to 8 bits, SPIRF contains up to 4 characters. The msbs are in bits 0, 8, 16, and 24.
For character lengths of 9 to 16 bits, SPIRF contains up to 2 characters. The msbs are in bits 0 and 16.
SPMODEx[REVx] does not affect the msb or lsb bit positions when reading the SPIRF register.
The user must read N bytes of SPIRF (1 N
FIFO. The user can read less bytes than the amount of data in the receive FIFO. For example, a 1-byte read
of SPIRF when configured for 8-bit characters with 4 characters of data in the receive FIFO results in the
3 unread characters shuffling down to the lower 24 bits of SPIRF in preparation for the following SPIRF
read.
The following tables show examples of the contents of SPIRF with various parameters set.
Freescale Semiconductor
0
MSB0
MSB0 Data 0 MS Byte Data 0 LS Byte LSB0
Offset 0x014
Reset
MSB0 Data 0 LSB0
0
0
0
0
1
Data 0 LS Byte
W
R
2
1
0
1
1
1
Figure 18-12. SPITF Example—SPMODEx[REVx]=1, SPMODEx[LENx]=15, MSB Sent First
3
Figure 18-11. SPITF Example—SPMODEx[REVx]=0, SPMODEx[LENx]=15, LSB Sent First
Data 0 MS Byte
Data 0 MS Byte
2
2
4
3
eSPI Receive FIFO Access Register (SPIRF)
5
4
3
6
5
7
4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
LSB0 MSB0
—
6
7
7
7
7
8
MSB1 Data 1 LSB1
8
Figure 18-15. SPIRF Example—SPMODEx[LENx]=10
Figure 18-16. SPIRF Example—SPMODEx[LENx]=15
8
Figure 18-14. SPIRF Example—SPMODEx[LENx]=3
8
8
Figure 18-13. eSPI Receive Data Register (SPIRF)
Data 0 LS Byte
9
Data 0 LS Byte
9
9
9
10 11 12 13 14
10 11 12 13 14 15 16 17 18 19 20 21 22
10
Data 0 MS Byte
10
11
11
14
12
LSB0 MSB1
—
15
—
LSB0 MSB1
4) that do not exceed the amount of data in the receive
15
15
15
All zeros
MSB2 Data 2 LSB2
MSB1
16
DATA
16
16
16
Data 1 LS Byte
17
17
17 18 19 20 21 22 23 24 25 26 27 28 29 30
17
Data 1 MS Byte
Data 1 MS Byte
18
Data 1 MS Byte
19
20
23
—
LSB1 MSB1
23
Data 1 LS Byte LSB1
23 24
Enhanced Serial Peripheral Interface
23
24
MSB3 Data 3 LSB3
24
24
Data 1 LS Byte
Data 1 LS Byte
25
25
25 26 27 28 29 30 31
Data 1 MS Byte
26
Access: Read only
26
27
27
30
28
—
—
LSB1
18-11
LSB1
31
31
31
31
31