MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 869

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-112
14.5.3.10.2 Receive Free Buffer Descriptor Pointer Registers 0–7
The RFBPTRn registers specify the location of the last free buffer descriptor in their respective ring. These
registers live in the same 32b address space – and must share the same 4 most significant bits – as RBPTRn.
That is, RFBPTRn and its associated RBPTRn must remain in the same 256MB page. Like RBPTRn,
whenever RBASEn is updated, RFBPTRn is initialized to the value of RBASEn. This indicates that the
ring is completely empty. As buffers are freed and their respective BDs are returned (by setting the EMPTY
bit) to the ring, software is expected to update this register. The eTSEC then performs modulo arithmetic
involving RBASEn, RBPTRn and RFBPTRn to determine the number of free BDs remaining in the ring.
If, at any stage, the value written to RFBPTRn matches that of the respective RBPTRn the eTSEC free BD
calculation assumes that the ring is now completely empty. For more information on the recommended use
of these registers, see
Figure 14-109
Table 14-113
Freescale Semiconductor
Offset eTSEC1:0x2_4C44+8 n ;
Reset
29–31
8–31
0–28 RFBPTR Pointer to the last free BD in RxBD Ring n . When RBASE n is updated, eTSEC initializes RFBPTR n
Bits
Bits
0–7
W
R
eTSEC3:0x2_6C44+8 n
0
FBTHR Free BD threshold. Minimum number of BDs required for normal operation. If the eTSEC calculated
Name
Name
LEN
—
describes the fields of the RQPRM register.
describes the fields of the RFBPTRn registers.
describes the definition for the RFBPTRn register.
(RFBPTR0–RFBPTR7)
number of free BDs drops below this threshold, link layer flow control is asserted.
Ring length. Total number of Rx BDs in this ring.
to the value in the corresponding RBASE n .
Software may update this register at any time to inform the eTSEC the location of the last free BD
in the ring. Note that the 3 least-significant bits of this register are read only and zero.
Reserved.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 14.6.6.1, “Back Pressure Determination through Free
Figure 14-109. RFBPTR0–RFBPTR7 Register Definition
Table 14-113. RFBPTR0–RFBPTR7 Field Descriptions
Table 14-112. RQPRM Field Descriptions
RFBPTR n
All zeros
Description
Description
Enhanced Three-Speed Ethernet Controllers
Buffers.”
Access: Read/Write
28 29
14-121
—
31