MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 405

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Writing to one of the four message registers (MSGR0–MSGR7) causes a messaging interrupt as directed
by the other message registers listed above. Reading a message register clears the messaging interrupt.
Note that a messaging interrupt can also be cleared by writing a one to the corresponding status field of
the PIC message status register (MSR), shown in
9.3.5.1
The message registers (MSGR0–MSGR7), shown in
Table 9-30
9.3.5.2
The MER, shown in
be set to enable interrupt generation when the corresponding message register is written.
When bits in MER are set to mask message interrupts, an interrupt is not generated if the message register
is written while it is masked in MER and the MER bit is then cleared. To mask the interrupt without loss,
set MIVPRn[MSK]. (See
MER should be set to 0x0000_000F at reset and then left unchanged during normal operation.
Freescale Semiconductor
Offset MSGR0: 0x1400; MSGR1: 0x1410; MSGR2: 0x1420; MSGR3: 0x1430
Reset
•
Offset 0x1500
Offset 0x2500
Reset
Reset
W
0–31
R
Bits
W
W
Section 9.3.7.6, “Messaging Interrupt Destination Registers
R
R
MSGR4: 0x2400; MSGR5: 0x2410; MSGR6: 0x2420; MSGR7: 0x2430
0
0
0
describes the MSGR registers.
Name
MSG
Message Registers (MSGR0–MSGR7)
Message Enable Register (MER)
Message. Contains the 32-bit message data.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Section 9.3.7.5, “Messaging Interrupt Vector/Priority Registers
9-29, contains the enable bits for each message register. The enable bit must
Figure 9-29. Message Enable Register (MER)
Figure 9-28. Message Registers (MSGRs)
Table 9-30. MSGR n Field Descriptions
—
—
Figure
All zeros
All zeros
All zeros
Figure
MSG
Description
9-30.
9-28, can contain a 32-bit message.
(MIDR0–MIDR7)”
Programmable Interrupt Controller (PIC)
Access: Read/Write
Access: Read/Write
27 28
27 28
Access: Read/Write
E3 E2 E1 E0
E7 E6 E5 E4
(MIVPRn).”)
29
29
30
30
31
31
9-35
31