MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1415

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 21-50
The buffer pointer list in the qTD is long enough to support a maximum transfer size of 20K bytes. This
case occurs when all five buffer pointers are used and the first offset is zero. A qTD handles a 16Kbyte
buffer with any starting buffer alignment.
The host controller uses the C_Page field as an index value to determine which buffer pointer in the list
should be used to start the current transaction. The host controller uses a different buffer pointer for each
physical page of the buffer. This is always true, even if the buffer is physically contiguous.
The host controller must detect when the current transaction spans a page boundary and automatically
move to the next available buffer pointer in the page pointer list. The next available pointer is reached by
incrementing C_Page and pulling the next page pointer from the list. Software must ensure there are
sufficient buffer pointers to move the amount of data specified in the Bytes to Transfer field.
Figure 21-50
and the C_Page field for a transfer size of 16383 bytes. C_Page is cleared. The upper 20-bits of Page 0
references the start of the physical page. Current Offset (the lower 12-bits of queue head Dword 7) holds
the offset in the page for example, 2049 (for example, 4096-2047). The remaining page pointers are set to
reference the beginning of each subsequent 4K page.
For the first transaction on the qTD (assuming a 512-byte transaction), the host controller uses the first
buffer pointer (page 0 because C_Page is cleared) and concatenates the Current Offset field. The 512 bytes
are moved during the transaction, the Current Offset and Total Bytes to Transfer are adjusted by 512 and
written back to the queue head working area.
During the 4th transaction, the host controller needs 511 bytes in page 0 and one byte in page 1. The host
controller will increment C_Page (to 1) and use the page 1 pointer to move the final byte of the transaction.
After the 4th transaction, the active page pointer is the page 1 pointer and Current Offset has rolled to one,
and both are written back to the overlay area. The transactions continue for the rest of the buffer, with the
Freescale Semiconductor
illustrates a nominal example of how System software would initialize the buffer pointers list
illustrates these requirements.
Pointer (Page 0)
Pointer (Page 1)
Pointer (Page 2)
Pointer (Page 3)
Pointer (Page 4)
Figure 21-50. Example Mapping of qTD Buffer Pointers to Buffer Pages
C_Page = 0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2047
4096
4096
4096
2048
Bytes to Transfer = 16383 bytes
The physical pages in memory
may or may not be physically
contiguous.
Page 0 = 2047
Page 1 = 4096
Page 2 = 4096
Page 3 = 4096
Page 4 = 2048
Total:
16383
Universal Serial Bus Interfaces
21-81