MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 756

BOARD DEV SYSTEM MPC8536E

MPC8536DS

Manufacturer Part Number
MPC8536DS
Description
BOARD DEV SYSTEM MPC8536E
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets

Specifications of MPC8536DS

Contents
Board, Software and Documentation
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Operating Supply Voltage
- 0.3 V to + 1.21 V
Maximum Operating Temperature
+ 105 C
Data Ram Size
32 KB
Interface Type
SPI, USB
Program Memory Type
DDR2, DDR3, SDRAM
Core Size
32 Bit
Program Memory Size
544KB
Cpu Speed
1.5GHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
0.95V To 1.05V
Rohs Compliant
Yes
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Enhanced Three-Speed Ethernet Controllers
14-8
TSEC_1588_CLK
TSEC n _TXD[7:4]
TSEC n _TXD[3:0]
TSEC n _TX_CLK
TSEC n _RX_ER
TSEC n _TX_ER
TSEC n _TX_EN
PULSE_OUT1
PULSE_OUT2
Signal Name
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC_1588_
TSEC_1588_
CLK_OUT
TRIG_IN0
TRIG_IN1
Table 14-1. eTSEC n Network Interface Signal Properties (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
GMII, MII, RMII—Receive error, input
TBI—RGC bit 9, input
FIFO—Receive error or receive frame control bit, input
RGMII, RTBI—Unused
MII—transmit clock, input
TBI—PMA receive clock 1, input
RMII—reference transmit and receive clock, input
FIFO—transmit clock, input
RGMII, RTBI—unused
GMII—transmit data bit 7:4, output
TBI—transmit code group (TCG) bit 7:4, output
FIFO—transmit data bit 7:4, output
MII, RGMII, RTBI, RMII—unused
GMII, MII—Transmit data bits 3:0, output
TBI—TCG bits 3:0, output
RGMII (TX_CLK rising)—Transmit data bits 3:0, output
RGMII (TX_CLK falling)—Transmit data bits 7:4, output
RTBI (TX_CLK rising)—TCG bits 3:0, output
RTBI (TX_CLK falling)—TCG bits 8:5, output
RMII—TXD[1:0] transmit data bits, output
RMII—TXD[3:2] unused, output
FIFO—Transmit data bits 3:0, output
GMII, MII—transmit error, output
RGMII, RTBI, RMII—unused, output driven zero
TBI—TCG bit 9, output
FIFO—transmit error or transmit frame control bit, output
GMII, MII, RMII—Transmit data valid, output
TBI—TCG bit 8, output
RGMII (TX_CLK rising)—Transmit data enabled, output
RGMII (TX_CLK falling)—Transmit error, output
RTBI (TX_CLK rising)—TCG bit 4, output
RTBI (TX_CLK falling)—TCG bit 9, output
FIFO—Transmit data valid or transmit control bit, output
1588—Clock input
External high precision timer reference clock input (chip external input pin).
1588—Clock output
Phase aligned timer clock divider output (chip external output pin).
1588—Trigger in 0
External timer trigger input 0. This is an asynchronous general purpose input (chip external
input pin).
1588—Trigger in 1
External timer trigger input 1. This is an asynchronous general purpose input (chip external
input pin).
1588—Pulse out 1
Timer pulse per period 1. It is phase aligned with 1588 timer clock (chip external output pin).
1588—Pulse out 2
Timer pulse per period 2. It is phase aligned with 1588 timer clock (chip external output pin).
Function
Freescale Semiconductor
Reset
State
0000
0000
0
0
0
0
0

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