MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 129

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The eSPI receiver and transmitter each have a FIFO of 32 bytes to support RapidS™ for Atmel™ devices.
The eSPI also supports Winbond™ dual-output read commands; in this mode the eSPI uses two bits in
parallel for read.
1.3.13
The SATA controllers have the following features:
1.3.14
Two integrated four-channel DMA controllers can transfer data between any I/O or memory ports or
between two devices or locations on the same port. The DMA controllers can be used as follows:
Freescale Semiconductor
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Support host SATA I per spec Rev 1.0a
— OOB
— Port multipliers
— ATAPI 6+
— Spread spectrum clocking on receive
Support for SATA II extensions
— Asynchronous notification
— Hot Plug including asynchronous signal recovery
— Link power management
— Native command queuing
— Staggered spin-up and port multiplier support
Support for SATA I and II data rates
— 1.5 & 3.0 Gbaud
Standard ATA master-only emulation
Includes ATA shadow registers
Implements SATA superset registers
— SError, SControl, SStatus
Interrupt driven
Power management support
Error handling and diagnostic features
— Far end/near end loopback
— Failed CRC error reporting
— Increased ALIGN insertion rates
— Scrambling and CONT override
To chain (both extended and direct) through local memory-mapped chain descriptors.
To handle misaligned transfers, as well as stride transfers and complex transaction chaining.
To specify local attributes such as snoop and L2 write stashing.
Serial ATA (SATA) Controllers
DMA Controller, I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C, DUART, eLBC
Overview
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