MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 911

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Tx_EN is negated after the FCS is sent. This notifies the PHY of the need to generate the illegal
Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS,
the Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. If the end of the
current buffer is reached and TxBD[L] is cleared (a frame is comprised of multiple buffer descriptors),
only TxBD[R] is cleared.
For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The Ethernet
controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each
frame, after each buffer, or after a specific buffer is sent. If TxBD[PAD/CRC] is set, the Ethernet controller
pads any frame shorter than 64 bytes with zero bytes to make up the minimum length.
To pause transmission, or rearrange the transmit queue, set DMACTRL[GTS]. This can be useful for
transmitting expedited data ahead of previously-linked buffers or for error situations. If this bit is set, the
eTSEC transmitter performs a graceful transmit stop. The Ethernet controller stops immediately if no
transmission is in progress or continues transmission until all queued frames in the Tx FIFO have been
disposed of. The IEVENT[GTSC] interrupt occurs once the graceful transmit stop operation is completed.
After the DMACTRL[GTS] is cleared, the eTSEC resumes transmission with the next frame.
While the eTSEC is in 10/100Mbps mode it sends bytes least-significant nibble first and each nibble is
sent lsb first. While it is in 1000Mbps mode it sends bytes LSB first.
14.6.3.4
The eTSEC Ethernet receiver is designed to work with little core intervention and can perform data
extraction, address recognition, CRC checking, short frame checking, and maximum frame-length
checking.
After a hardware reset, the software driver clears the RSTAT register and sets MACCFG1[RX_EN]. The
Ethernet receiver is enabled and immediately starts processing receive frames. The MAC checks for when
TSECn_RX_DV is asserted and as long as TSECn_COL remains negated (full-duplex mode ignores
TSECn_COL), the MAC looks for the start of a frame by searching for a valid preamble/SFD (start of
frame delimiter) header, which is stripped (unless MACCFG2[PreAM RxEN] is set) and the frame begins
to be processed. If a valid header is not found, the frame is ignored.
If the receiver detects the first bytes of a frame, the eTSEC controller begins to perform the frame
recognition function through destination address (DA) recognition (see
Recognition”). Based on this match the frame can be accepted or rejected. The receiver can filter frames
based on individual (unicast), group (multicast), and broadcast addresses. Because Ethernet receive frame
data is not written to memory until the internal frame recognition algorithm is complete, system bus usage
is not wasted on frames unwanted by this station.
If a frame is accepted, the Ethernet controller fetches the receive buffer descriptor (RxBD) from either
queue 0 or the queue determined by the filer. If the RxBD is not being used by software (RxBD[E] is set),
the eTSEC starts transferring the incoming frame. RxBD[F] is set for the first RxBD used for any
particular receive frame. If the current RxBD is not available for the received frame, a receive busy error
condition is raised in IEVENT[BSY].
Freescale Semiconductor
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MACCFG2[PAD/CRC] is set
MACCFG2[CRC] is set
Gigabit Ethernet Frame Reception
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enhanced Three-Speed Ethernet Controllers
Section 14.6.3.7, “Frame
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