MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1615

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A.1.4
Freescale Semiconductor
0x140–
0x150–
0x0CC
Offset
0x08C
0x0C0
0x0C4
0x0C8
0x10C
0x11C
0x14C
0x15F
0x000
0x008
0x010
0x018
0x080
0x084
0x088
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x144
0x148
0x160
0x164
DDR Memory Controller
CS0_BNDS—Chip select 0 memory bounds
CS1_BNDS—Chip select 1 memory bounds
CS2_BNDS—Chip select 2 memory bounds
CS3_BNDS—Chip select 3 memory bounds
CS0_CONFIG—Chip select 0 configuration
CS1_CONFIG—Chip select 1 configuration
CS2_CONFIG—Chip select 2 configuration
CS3_CONFIG—Chip select 3 configuration
CS0_CONFIG_2—Chip select 0 configuration 2
CS1_CONFIG_2—Chip select 1 configuration 2
CS2_CONFIG_2—Chip select 2 configuration 2
CS3_CONFIG_2—Chip select 3 configuration 2
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration
2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration
2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval
configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Reserved
DDR_INIT_ADDR—DDR training initialization address
DDR_INIT_EXT_ADDRESS—DDR training initialization
extended address
Reserved
TIMING_CFG_4— DDR SDRAM timing configuration 4
TIMING_CFG_5— DDR SDRAM timing configuration 5
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DDR Memory Controller—Block Base Address 0x0_2000
Table A-4. DDR Memory Controller Registers
Register
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
Section/Page
8.4.1.10/8-29
8.4.1.11/8-29
8.4.1.12/8-30
8.4.1.13/8-33
8.4.1.14/8-33
8.4.1.15/8-34
8.4.1.16/8-34
8.4.1.17/8-35
8.4.1.18/8-36
8.4.1.19/8-37
8.4.1.1/8-12
8.4.1.1/8-12
8.4.1.1/8-12
8.4.1.1/8-12
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.3/8-15
8.4.1.3/8-15
8.4.1.3/8-15
8.4.1.3/8-15
8.4.1.4/8-16
8.4.1.5/8-17
8.4.1.6/8-19
8.4.1.7/8-21
8.4.1.8/8-23
8.4.1.9/8-26
—
—
A-3