MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 693

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The basic GPCM write timing parameters that may be set by the ORn attributes are shown in

The write access cycle commences upon latching of the memory address (LALE negated), and concludes

when LCSn returns high. LBCTL remains stable for the entire cycle to drive data onto any secondary data

bus. Write data becomes invalid following the falling edge of TA. LWE may, in some cases, negate high

before the end of the write access to provide additional hold time for the external memory.

Freescale Semiconductor

Option Register Attributes

GPCM Write Signal Timing

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

Table 13-32. GPCM Read Control Signal Timing (continued)

= Write cycle time.

= Address valid to write enable time.

= Address valid to write chip-select time.

Figure 13-37. GPCM General Write Timing Parameters

Signal Timing (LCLK clock cycles)

Latched Address

= Write enable negated time wrt chip-selec

= Write chip-select assertion period.

Enhanced Local Bus Controller