MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1478

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.9.1.5
The operational models are well defined for the behavior of the transaction translator (see Universal Serial
Bus Revision 2.0 Specification) and for the EHCI controller moving packets between system memory and
a USB-HS hub. Since the embedded transaction translator exists within the USB module there is no
physical bus between EHCI host controller driver and the USB FS/LS bus. These sections will briefly
discuss the operational model for how the EHCI and transaction translator operational models are
combined without the physical bus between. The following sections assume the reader is familiar with
both the EHCI and USB 2.0 transaction translator operational models.
21.9.1.5.1
The EHCI operational model uses the concept of H-frames and B-frames to describe the pipeline between
the Host (H) and the Bus (B). The embedded transaction translator shall use the same pipeline algorithms
specified in the Universal Serial Bus Revision 2.0 Specification for a Hub-based transaction translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the stored periodic transfers
are complete. As an example of the microframe pipeline implemented in the embedded transaction
translator, all periodic transfers that are tagged in EHCI to execute in H-frame 0 will be ready to execute
on the bus in B-frame 0.
It is important to note that when programming the S-mask and C-masks in the EHCI data structures to
schedule periodic transfers for the embedded transaction translator, the EHCI host controller driver must
follow the same rules specified in EHCI for programming the S-mask and C-mask for downstream
Hub-based transaction translators.
Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous
transfers are opportunistic in that they shall execute whenever possible and their operation is not tied to
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2. siTD (for direct attach FS)—Periodic (ISO Endpoint)
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Hub Address = 0
Transactions to direct attached device/hub.
— QH.EPS = Port Speed
Transactions to a device downstream from direct attached FS hub.
— QH.EPS = Downstream Device Speed
Maximum Packet Size must be less than or equal 64 or undefined behavior may result.
All FS ISO transactions:
— Hub Address = 0
— siTD.EPS = 00 (full speed)
Maximum Packet Size must less than or equal to 1023 or undefined behavior may result.
Operational Model
When QH.EPS = 01 (LS) and PORTSC[PSPD] = 00 (FS), a LS-pre-pid will
be sent before the transmitting LS traffic.
Microframe Pipeline
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Freescale Semiconductor