MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1373

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.26 System Interface Control Register (SI_CTRL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The
system interface control register (SI_CTRL) controls various functions pertaining to the internal system
interface.
21.3.2.27 USB General Purpose Register (CONTROL)—Non-EHCI
Note that this register uses big-endian byte ordering and is not defined in the EHCI specification. The USB
general purpose (CONTROL) register contains the general-purpose IP control register outputs and is
shown in
Freescale Semiconductor
Offset 0x410
Reset
Offset 0x500
28–30
Reset
Reset
0–26
Bits
27
31
W
R
W
W
R
R
0
16
0
rd_prefetch_val Selects whether 32 bytes or 64 bytes are fetched during burst read transactions at the system
Figure
err_disable
Name
—
—
21-33.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared
When this bit is set, it causes the controller to ignore system bus errors. If cleared the controller
responds according to the values set in USBSTS[SEI] and USBINT[SEE].
0 enable
1 disable
Reserved, should be cleared
interface. When this input is LOW 64 bytes are fetched and when it is HIGH 32 bytes are fetched.
The setting of rd_prefetch_val must match the setting of the larger of TXPBURST and RXPBURST
fields in the BURSTSIZE register. If either of these fields is 64 bytes, then rd_prefetch_val must be
left cleared. Otherwise, this value should be set.
0 64-byte fetch.
1 32-byte fetch.
Figure 21-32. System Interface Control Register (SI_CTRL)
Figure 21-33. USB General-Purpose Register (CONTROL)
Table 21-34. SI_CTRL Register Field Descriptions
—
—
—
All zeros
All zeros
All zeros
Description
26
disable
err_
27
28
Universal Serial Bus Interfaces
28
USB_
EN
29
—
Access: Read/Write
INT_EN
WU_
14
30
30
Access: Mixed
rd_prefetch
WU_INT
INT_EN
ULPI_
_val
31
15
31
21-39