MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 64

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
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lxiv
UPM Read Access Data Sampling...................................................................................... 13-88
Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)............................ 13-102
Local Bus to 8-Bit FCM Device Interface .......................................................................... 13-60
FCM Basic Page Read Timing
FCM Buffer RAM Memory Map for Small-Page (512-byte page) NAND Flash Devices 13-62
FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND Flash Devices . 13-63
FCM ECC Calculation ........................................................................................................ 13-64
ECC Layout for LBCR[EPAR] = 0 (~ represents logical negation) ................................... 13-64
ECC Placement in NAND Flash Spare Regions in Relation to FMR[ECCM] .................. 13-65
FCM Instruction Sequencer Mechanism............................................................................. 13-65
Timing of FCM Command/Address and Write Data Cycles
Example of FCM Command and Address Timing with Minimum Delay Parameters
Example of FCM Command and Address Timing with Relaxed Parameters
FCM Delay Prior to Sampling LFRB State ........................................................................ 13-70
FCM Read Data Timing
FCM Read Data Timing with Extended Hold Time
FCM Buffer RAM Memory Map During Boot Loading .................................................... 13-73
User-Programmable Machine Functional Block Diagram.................................................. 13-75
RAM Array Indexing .......................................................................................................... 13-76
Memory Refresh Timer Request Block Diagram ............................................................... 13-77
UPM Clock Scheme............................................................................................................ 13-80
RAM Array and Signal Generation .................................................................................... 13-80
RAM Word Fields ............................................................................................................... 13-81
LCSn Signal Selection ........................................................................................................ 13-84
LBS Signal Selection .......................................................................................................... 13-85
Effect of LUPWAIT Signal ................................................................................................. 13-89
Multiplexed Address/Data Bus for 32-Bit Addressing ...................................................... 13-91
Local Bus Peripheral Hierarchy for High Bus Speeds........................................................ 13-91
GPCM Address Timings ..................................................................................................... 13-92
GPCM Data Timings........................................................................................................... 13-92
Interface to Different Port-Size Devices ............................................................................. 13-94
Single-Beat Read Access to FPM DRAM ........................................................................ 13-100
Single-Beat Write Access to FPM DRAM ....................................................................... 13-101
Refresh Cycle (CBR) to FPM DRAM .............................................................................. 13-103
Exception Cycle ................................................................................................................ 13-104
(PGS = 1, CSCT = 0, CST = 0, CHT = 1, RST = 1, SCY = 0, TRLX = 0, EHTR = 1) 13-60
(for TRLX = 0, CHT = 0, CST = 1, SCY = 1) ............................................................... 13-68
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0) ............................................................... 13-69
(for TRLX = 1, CHT = 0, CST = 1, SCY = 2) ............................................................... 13-70
(for TRLX = 0, RST = 0, SCY = 1) ............................................................................... 13-71
(for TRLX = 0, EHTR = 1, RST = 1, SCY = 1)............................................................. 13-72
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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