MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 782

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Table 14-10
14-34
10–12
16–27
Bits
0–1
4–6
13
14
15
28
29
2
3
7
8
9
EBERRDIS Ethernet controller bus error disable.
XFUNDIS
BABTDIS
BSYDIS
TXEDIS
CRLDIS
FIRDIS
FIQDIS
LCDIS
Name
—
—
—
—
—
describes the fields of the EDIS register.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Busy disable.
0 Allow eTSEC to report IEVENT[BSY] status and halt buffer descriptor queue if BSY condition occurs.
1 Do not set IEVENT[BSY] and do not halt buffer descriptor queue if BSY condition occurs.
0 Allow eTSEC to report IEVENT[EBERR] status and halt buffer descriptor queue if EBERR condition
1 Do not set IEVENT[EBERR] and do not halt buffer descriptor queue if EBERR condition occurs.
Reserved
Babbling transmit error disable.
0 Allow eTSEC to report IEVENT[BABT] status and set the buffer descriptor TR field.
1 Do not set IEVENT[BABT] nor the buffer descriptor TR field.
Reserved
Transmit error disable.
0 Allow eTSEC to report IEVENT[TXE] status.
1 Do not set IEVENT[TXE] if TXE condition occurs.
Reserved
Late collision disable.
0 Allow eTSEC to report IEVENT[LC] status, set the buffer descriptor LC field, and halt buffer descriptor
1 Do not set IEVENT[LC] nor the buffer descriptor LC field, and do not halt buffer descriptor queue if
Collision retry limit disable.
0 Allow eTSEC to report IEVENT[CRL] status, set the buffer descriptor RL field, and halt buffer
1 Do not set IEVENT[CRL] nor the buffer descriptor RL field, and do not halt buffer descriptor queue if
Transmit FIFO underrun disable.
0 Allow eTSEC to report IEVENT[XFUN] status, set the buffer descriptor UN field, and halt buffer
1 Do not set IEVENT[XFUN] nor the buffer descriptor UN field, and do not halt buffer descriptor queue
Reserved
Filer invalid result error disable.
0 Allow eTSEC to report IEVENT[FIR] status.
1 Do not set IEVENT[FIR] if eTSEC fails to reach a definite filer result when attempting to file a received
Filed frame to invalid queue error disable.
0 Allow eTSEC to report IEVENT[FIQ] status.
1 Do not set IEVENT[FIQ] if eTSEC attempts to file a received frame to an invalid (disabled) RxBD ring,
occurs.
queue if LC condition occurs.
LC condition occurs.
descriptor queue if CRL condition occurs.
CRL condition occurs.
descriptor queue if XFUN condition occurs.
if XFUN condition occurs.
frame, but discard the frame silently.
but discard the frame silently.
Table 14-10. EDIS Field Descriptions
Description
Freescale Semiconductor