MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 722

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
13.4.4.3
RAM word fields specify the value of the various external signals at a granularity of up to four values for
each bus clock cycle. The signal timing generator causes external signals to behave according to timing
specified in the current RAM word. ach bit in the RAM word relating to LCSn and LBS timing specifies
the value of the corresponding external signal at each quarter phase of the bus clock.
The division of UPM bus cycles into phases is shown in
13.4.4.4
The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in
at the bottom of the figure are UPM outputs. The selected LCSn is for the bank that matches the current
address. The selected LBS is for the byte lanes read or written by the access.
13.4.4.4.1
The RAM word is a 32-bit microinstruction stored in one of 64 locations in the RAM array. It specifies
timing for external signals controlled by the UPM.
and BSTn bits determine the state of UPM signals LCSn and LBS[0:3] at each quarter phase of the bus
clock.
13-80
Clock Phases
T1, T2, T3, T4
Current Bank
LCLK
UPM Signal Timing
RAM Array
T1
T2
T3
T4
RAM Words
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
LCS[0:7]
Selector
CS Line
Figure 13-65. RAM Array and Signal Generation
LGPL0
Figure 13-64. UPM Clock Scheme
External Signals Timing Generator
LGPL1
RAM Array
LGPL2 LGPL3 LGPL4 LGPL5
32 Bits
Figure 13-39
Figure
13-64.
shows the RAM word fields. he CSTn
LBS[0:3]
Byte Select
64 deep
Logic
Figure
BRn[PS], LA[30:31]
Freescale Semiconductor
13-65. The signals