MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1218

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Serial Peripheral Interface
18.2.1
Table 18-1
18.2.2
Table 18-2
18-4
SPI_CS[0:3] O eSPI slave select outputs
SPI_MISO
SPI_MOSI
SPI_CLK
Signal
lists signal properties.
describes the signals in detail.
Overview
Detailed Signal Descriptions
I/O
O master output slave input or 2nd master input slave output for Winbond dual output read
O Serial clock out
I master input slave output
Meaning
Meaning
Meaning
Meaning
SPI_CS[0:3]
Timing Assertion—according to the SPI_CLK assertion/negation/in the middle of phase (depends on
Timing Assertion—according to the SPI_CLK assertion/negation/in the middle of phase (depends on
Timing Assertion/Negation—during frame reception/transmission
Timing Assertion—a predefined time before frame starts, during frame transmission/reception,
SPI_MISO
SPI_MOSI
State
State
State
State
SPI_CLK
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Asserted—the data that has been received from the eSPI is high
Negated—the data that has been received from the eSPI is low
Negation—according to the SPI_CLK assertion/negation/in the middle of phase (depends on the
Asserted—the data that has been transmitted from/to the eSPI is high
Negated—the data that has ben transmitted from/to the eSPI is low
Negation—according to the SPI_CLK assertion/negation/in the middle of phase (depends on the
Assertion/Negation according to SPMODEx[PM,DIV16] register rate configuration
Asserted— slave 0, 1, 2, 3 is selected and master controls transmission/reception
Negated—idle state
a predefined time after frame ends
Negation—when master is idle or controls another slave
the SPMODEx configuration register).
SPMODEx configuration register)
the SPMODEx configuration register).
SPMODEx configuration register)
master input slave output
Winbond dual output read
eSPI slave select outputs
master output slave input or second master input slave output for
ioutput serial clock connected to the other SPI_CLK
Table 18-2. Detailed Signal Descriptions
Table 18-1. Signal Properties
Description
Function
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