MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 558

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.5.10 KEU IV_1 Register (KEUIV1)
The KEU IV_1 register is a general purpose IV register, shown in
initialization phase of the f8 algorithms for 3GPP, GSM A5/3, EDGE A5/3, GPRS GEA3, and f9 algorithm
for 3GPP. The appropriate value as defined by the standards for each algorithm must be written before a
new message is started.
After the initialization phase has been completed, the KEU IV_1 register is no longer used for the
remainder of f8 processing. However, if 3GPP f9 is selected because the KEU IV_1 register contains the
direction bit as defined by the 3GPP standard, the KEU IV_1 register must be written back during context
switches to complete the generation of the 3GPP MAC.
Table 10-58
The following figure shows how the KEU IV_1 register can be differentiated for different applications.
10-128
(GEA3)
EDGE
GPRS
(A5/3)
(A5/3)
3GPP
32–36
38–39
40–47
48–63
GSM
0–31
Bits
37
(f8)
Reset
Field
Addr
R/W
0
32 bit Frame Dependent Input
Field
CC
CB
CD
CA
CE
0
describes the KEU IV_1 register fields.
0000000000 || Count
0
Count
Bearer
Direction bit
00
00000000
000000000000000
3GPP Definition
Count
Count
Value
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
CC
Table 10-58. KEU IV_1 Register Fields Description
31
Count
00000
0
00
00001111
0000000000000000
Figure 10-73. KEU IV_1 Register
GSM A5/3 Definition EDGE A5/3 Definition
32
31
Bearer
00000
00000
00000
32
36
CB
KEU 0x3_E100
36
R/W
Dir.
37
0
0
0
0
0000000000 | | Count
00000
0
00
11110000
0000000000000000
CD
37
38
00
00
00
00
38
39
00
Figure
39
40
00000000
00001111
11110000
11111111
10-73, is used during the
40
CA
Frame dependent input value
(32-bits)
00000
0
00
11111111
0000000000000000
47
GPRS GEA3 Definition
47
Freescale Semiconductor
48
000000000000000
000000000000000
000000000000000
000000000000000
48
CE
63
63