MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 242

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
Figure 6-20
Table 6-17
Figure 6-21
condition exists, the L2 signals an interrupt to the core through the internal int signal.
6-22
Offset 0x2_0E44
Reset
0–26
Offset 0x2_0E48
Reset
Bits
27
28
29
30
31
W
W
R
R
0
MBECCDIS Multiple-bit ECC error disable. Note that uncorrectable read errors may cause the assertion of
0
SBECCDIS Single-bit ECC error disable
L2CFGDIS
TPARDIS
Name
—
—
describes L2ERRDIS fields.
shows the L2 error disable register (L2ERRDIS).
shows the L2 error interrupt enable register (L2ERRINTEN). When an enabled error
Reserved
Tag parity error disable
0 Tag parity error detection enabled
1 Tag parity error detection disabled
core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by
clearing HID1[RFXE]). If RFXE is zero and this error occurs, MBECCDIS must be cleared and
L2ERRINTEN[MBECCINTEN] must be set to ensure that an interrupt is generated. For more information,
see the reference manual for the e500 core.
0 Multiple-bit ECC error detection enabled
1 Multiple-bit ECC error detection disabled
0 Single-bit ECC error detection enabled
1 Single-bit ECC error detection disabled
Reserved
L2 configuration error disable
0 L2 configuration error detection enabled
1 L2 configuration error detection disabled
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 6-21. L2 Error Interrupt Enable Register (L2ERRINTEN)
Figure 6-20. L2 Error Disable Register (L2ERRDIS)
—
—
Table 6-17. L2ERRDIS Field Descriptions
All zeros
All zeros
26
Description
TPARINTEN MBECCINTEN SBECCINTEN
26
27
TPARDIS MBECCDIS0 SBECCDIS — L2CFGDIS
27
28
28
29
Freescale Semiconductor
29
Access: Read/Write
Access: Read/Write
—
30
30
L2CFGINTEN
31
31