MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1072

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
When the initiator intends to complete only one more data transfer (which could be immediately after the
address phase), PCI_FRAME is negated and PCI_IRDY is asserted (or kept asserted), indicating the
initiator is ready. After the target indicates the final data transfer (by asserting PCI_TRDY), the PCI bus
may return to the idle state (both PCI_FRAME and PCI_IRDY are negated) unless a fast back-to-back
transaction is in progress. In the case of a fast back-to-back transaction, an address phase immediately
follows the last data phase.
16.4.2.2
A PCI bus command is encoded in the PCI_C/BE[3:0] signals during the address phase of a PCI
transaction. The bus command indicates to the target the type of transaction the initiator is requesting.
Table 16-47
16-46
BE[3:0]
PCI_C/
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
Interrupt-
acknowledge
Special cycle
I/O-read
I/O-write
Reserved
Reserved
Memory-read
Memory-write
Reserved
Reserved
Configuration-
read
Configuration-
write
Memory-read-
multiple
Dual-address-
cycle
Command
PCI Bus
describes the PCI bus commands implemented by the device.
PCI Bus Commands
1
1
1
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Supported
Initiator
as an
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Agent mode
Agent mode
as a Target
Supported
Table 16-47. PCI Bus Commands
only
only
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
A read (implicitly addressing the system interrupt controller). Only one
device on the PCI bus should respond to this command; others ignore
it. See
more information.
Provides a way to broadcast select messages to all devices on the PCI
bus. See
information.
Accesses agents mapped into the PCI I/O space.
Accesses agents mapped into the PCI I/O space.
—
—
Accesses either local memory or agents mapped into PCI memory
space, depending on the address. When a PCI master issues this
command to local memory, the PCI controller (the target) fetches data
from the requested address to the end of the cache line (32 bytes) from
local memory, even though all of the data may not be requested by (or
sent to) the initiator.
Accesses either local memory or agents mapped into PCI memory
space, depending on the address.
—
—
Accesses the 256-byte configuration space of a PCI agent. A specific
agent is selected when its IDSEL signal is asserted during the address
phase. See
Similar to the memory-read command, but also causes a prefetch of the
next cache line (32 bytes).
Used to transfer a 64-bit address (in two 32-bit address cycles) to 64-bit
addressable devices.
Section 16.4.2.12.1, “Interrupt-Acknowledge Transactions,”
Section 16.4.2.12.2, “Special-Cycle Transactions,”
Section 16.4.2.11, “Configuration Cycles,”
Definition
Freescale Semiconductor
for details.
for more
for