MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1425

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pointer. At the same time, it sets an internal flag indicating that it is now in Recovery Path mode (the
recovery path is annotated in
traversing data structures on the recovery path and executing only those bus transactions as noted above,
on the recovery path until it reaches Restore FSTN (Restore-N). Restore-N.Back Path Link Pointer.T-bit
is set (definition of a Restore indicator), so the host controller exits Recovery Path mode by clearing the
internal Recovery Path mode flag and commences (restores) schedule traversal using the saved value of
the Save-Place FSTN's Normal Path Link Pointer (for example, Save-N.Normal Path Link Pointer). The
nodes traversed during these micro-frames include: {8
4
In frame N+1 (micro-frames 2-7), when the host controller encounters Save-Path FSTN Save-N, it
unconditionally follows Save-N.Normal Path Link Pointer. The nodes traversed during these micro-frames
include: {8
21.6.12.2.3 Software Operational Model for FSTNs
Software must create a consistent, coherent schedule for the host controller to traverse. When using
FSTNs, system software must adhere to the following rules:
Software should make the schedule as efficient as possible. What this means in this context is that software
should have no more than one Save-Place FSTN reachable in any single frame. Note there will be times
when two (or more, depending on the implementation) could exist as full-/low-speed footprints change
with bandwidth adjustments. This could occur, for example when a bandwidth rebalance causes system
software to move the Save-Place FSTN from one poll rate level to another. During the transition, software
must preserve the integrity of the previous schedule until the new schedule is in place.
Freescale Semiconductor
3
, 2
•
•
•
•
1
, Restore-N, 10 ...}.
Each Save-Place indicator requires a matching Restore indicator.
The Save-Place indicator is an FSTN with a valid Back Path Link Pointer and T-bit equal to zero.
Note that Back Path Link Pointer[Typ] field must be set to indicate the referenced data structure is
a queue head. The Restore indicator is an FSTN with its Back Path Link Pointer[T] bit set.
A Restore FSTN may be matched to one or more Save-Place FSTNs. For example, if the schedule
includes a poll-rate 1 level, then system software only needs to place a Restore FSTN at the
beginning of this list in order to match all possible Save-Place FSTNs.
If the schedule does not have elements linked at a poll-rate level of one, and one or more
Save-Place FSTNs are used, then System Software must ensure the Restore FSTN's Normal Path
Link Pointer's T-bit is set, as this will be use to mark the end of the periodic list.
When the schedule does have elements linked at a poll rate level of one, a Restore FSTN must be
the first data structure on the poll rate one list. All traversal paths from the frame list converge on
the poll-rate one list. System software must ensure that Recovery Path mode is exited before the
host controller is allowed to traverse the poll rate level one list.
A Save-Place FSTN's Back Path Link Pointer must reference a queue head data structure. The
referenced queue head must be reachable from the previous frame list location. In other words, if
the Save-Place FSTN is reachable from frame list offset N, then the FSTN's Back Path Link Pointer
must reference a queue head that is reachable from frame list offset N-1.
3.0
, 8
3.1
, 8
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
3.2
, Save-A, 4
Figure 21-54
3
, 2
1
, Restore-N, 1
with a large dashed line). The host controller continues
0
3.0
...}.
, 8
3.1
, 8
3.2
, Save-A, 8
2.2
, 8
Universal Serial Bus Interfaces
2.3
, 4
2
, 2
0
, Restore-N,
21-91