MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1085

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

layout shown in
header specific to the PCI controller is described in
Table 16-49
provided in the PCI Local Bus Specification, Rev. 2.2.
Freescale Semiconductor
Offset (Hex)
0x10–0x27
Address
0x0C
0x0D
0x0E
0x00
0x02
0x04
0x06
0x08
0x09
0x0F
Max_Lat
BIST
summarizes the configuration header registers. Detailed descriptions of these registers are
Base address registers
Figure
Register Name
Cache line size
Latency timer
Header type
Revision ID
Class code
Command
Vendor ID
Device ID
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Status
Subsystem ID
BIST
Device ID
16-58. The rest of the 256-byte configuration space is device-specific. The PCI
Status
Table 16-49. PCI Configuration Space Header Summary
Figure 16-58. Standard PCI Configuration Header
Header Type
Class Code
Identifies the manufacturer of the device (assigned by the PCI SIG (special-interest
group) to ensure uniqueness).
Identifies the particular device (assigned by the vendor).
Provides coarse control over a device’s ability to generate and respond to PCI bus
cycles
Records status information for PCI bus-related events
Specifies a device-specific revision code (assigned by vendor)
Identifies the generic function of the device and (in some cases) a specific
register-level programming interface
Specifies the system cache line size in 32-bit units
Specifies the value of the latency timer in PCI bus clock units for the device when
acting as an initiator
Bits 0–6 identify the layout of bytes 0x10–0x3F; bit 7 indicates a multifunction device.
The most common header type (0x00) is shown in
Optional register for control and status of built-in self test (BIST)
Address mapping information for memory and I/O space
Min_Gnt
Expansion ROM Base Address
Base Address Registers
Reserved
Reserved
Reserved
Section 16.3.2, “PCI Configuration Header.”
Latency Timer
Interrupt Pin
Description
Subsystem Vendor ID
Command
Vendor ID
Figure 16-58
Cache Line Size
Interrupt Line
Revision ID
Address Offset (Hex)
and in this table.
PCI Bus Interface
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
16-59