MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 564

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Table 10-60
10-134
Reset
Field
Addr
R/W
The following bits are described for information only. They are not under direct user control.
62-63
0–50
Bits
Bits
59
60
61
51
52
53
0
describes MDEU Mode Register fields in new configuration.
MDEU_B
HMAC
—
Name
Name
STIB
ALG
INIT
PD
—
—
Table 10-59. MDEU Mode Register in Old Configuration (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-84. MDEU Mode Register in New Configuration
50
Table 10-60. MDEU Mode Register in New Configuration
Initialization Bit: Most operations require this bit to be set. Cleared only for operations that
load context from a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash
1 Do an algorithm-specific initialization of the digest registers.
Specifies whether to perform an HMAC operation:
0 Normal operation
1 Perform an HMAC operation. This requires a key and key length. If this is set then the
This bit must be programmed opposite to the CONT bit.
Message Digest algorithm selection
00 if MDEU-B, then SHA-384. If MDEU-A, then SHA-160 algorithm (full name for SHA-1)
01 SHA-256 algorithm
10 if MDEU-B, then SHA-512. If MDEU-A, then MD5 algorithm
11 SHA-224 algorithm
Reserved
Selects which algorithms are enabled by the ALG bits.
0 MDEU-A enables selection between SHA-1, SHA-256, MD5, and SHA-224
1 MDEU-B enables selection between SHA-384, SHA-256, SHA-512, and SHA-224.
Reserved, must be cleared.
SSL/TLS inbound, block cipher:
0 Normal operation.
1 Special operation only for SSL/TLS inbound, block cipher. Upon receiving end of
MDEU_B —
context pointer in the descriptor. When the data to be hashed is spread across multiple
descriptors, this bit must be 0 on all but the first descriptor.
SMAC bit should be 0.
message notification, the MDEU performs a calculation involving the last valid byte of
data written into its input FIFO (which is Pad Length) to compute a final data size. The
MDEU then processes the amount of data specified by this data size, and completes the
message digest.
51
52
STIB NEW=1
53
MDEU 0x3_6000
54
R/W
0
—
55
Description
Description
CONT CICV SMAC INIT HMAC EALG
56
57
58
59
Freescale Semiconductor
60
61
62
ALG
63