MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 590

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Table 10-75
10.7.8.7
The RNGU end of message register (shown in
start the RNGU. A write of any value to this register causes the RNGU to begin to produce random
numbers in the FIFO.
10-160
Address 0x3_A050
Offset 0x3_A038
Reset
Reset
52–55
58–61
0–50
W
Bits
R
51
56
57
62
63
W
R
0
0
describes RNGU interrupt status register fields.
RNGU End of Message Register
Name
OFU
ME
AE
—
IE
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-75. RNGU Interrupt Mask Register Field Descriptions
Reserved
Internal Error. An internal processing error was detected while generating random
numbers. This error is no longer maskable and can only be cleared by setting one of the
reset bits in the Reset Control Register
0 Internal error enabled
1 Internal error disabled
Reserved
Mode Error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address Error. An illegal read or write address was detected within the RNGU address
space.
0 Address error enabled
1 Address error disabled
Reserved
Output FIFO Underflow. RNGU Output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
Figure 10-109. RNGU End of Message Register
Figure 10-108. RNGU Interrupt Mask Register
—
Figure
All zeros
All zeros
20-192) is a write-only register that can be used to
—
Description
50
IE
51 52
—
55
ME
56
Freescale Semiconductor
AE
57
Access: Write only
Access: Read only
58
—
61
OFU
62
63
—
63