MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1157

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-60
17.3.8.3.8
The PCI Express secondary status register is shown in
may be masked by corresponding bits in the secondary status interrupt mask register
(PEX_SS_INTR_MASK) and that by default all of the errors are masked. See
“Secondary Status Interrupt Mask Register (RC-Mode
Table 17-63
Freescale Semiconductor
Offset 0x1E
Reset
10–9
Bits
7–0
15
14
13
12
11
8
W w1c
R DPE
15
Bits
7–4
3–0
MDPE
Name
RMA
DPE
SSE
RTA
STA
describes the I/O limit register fields.
describes the PCI Express secondary status register fields.
—
—
SSE
w1c
14
PCI Express Secondary Status Register—0x1E
Address Decode Type Specifies the number of I/O address bits.
Table 17-63. PCI Express Secondary Status Register Field Description
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
I/O Limit Address
RMA
w1c
13
Detected parity error. This bit is set whenever the secondary side receives a poisoned TLP regardless
of the state of the parity error response bit.
Signaled system error. This bit is set when a device sends a ERR_FATAL or ERR_NONFATAL message,
provided the SERR enable bit in the command register is set to enable reporting.
Received master abort. This bit is set when the secondary side receives an unsupported request (UR)
completion.
Received target abort. This bit is set when the secondary side receives a completer abort (CA)
completion.
Signaled target abort. This bit is set when the secondary side issues a CA completion.
Reserved
Master data parity error. This bit is set when the parity error response bit is set and the secondary side
requestor receives a poisoned completion or poisons a write request. If the parity error response bit is
cleared, this bit is never set.
Reserved
Table 17-62. PCI Express I/O Limit Register Field Description
Name
Figure 17-65. PCI Express Secondary Status Register
RTA
w1c
12
STA
w1c
11
Specifies bits 15:12 of the I/O space ending address
0x00 16-bit I/O address decode
0x01 32-bit I/O address decode
All other settings reserved.
10
—
9
MDPE
w1c
8
All zeros
Figure
Only)—0x5A0,” for more information.
Description
7
17-65. Note that the errors in this register
Description
Section 17.3.10.20,
PCI Express Interface Controller
—
Access: Mixed
17-61
0