MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1436

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Software must apply the following rules when calculating the schedule and linking the schedule data
structures into the periodic schedule:
21.6.12.3.2 Tracking Split Transaction Progress for Isochronous Transfers
Isochronous endpoints do not employ the concept of a halt on error, however the host controller does
identify and report per-packet errors observed in the data stream. This includes schedule traversal
problems (skipped micro-frames), timeouts and corrupted data received.
In similar kind to interrupt split-transactions, the portions of the split transaction protocol must execute in
the micro-frames they are scheduled. The queue head data structure used to manage full- and low-speed
interrupt has several mechanisms for tracking when portions of a transaction have occurred. Isochronous
transfers use siTDs for their transfers and the data structures are only reachable using the schedule in the
exact micro-frame in which they are required (so all the mechanism employed for tracking in queue heads
is not required for siTDs). Software has the option of reusing siTD several times in the complete periodic
schedule. However, it must ensure that the results of split transaction N are consumed and the siTD
re-initialized (activated) before the host controller gets back to the siTD (in a future micro-frame).
Split-transaction isochronous OUTs utilize a low-level protocol to indicate which portions of the split
transaction data have arrived. Control over the low-level protocol is exposed in an siTD using the fields
Transaction Position (TP) and Transaction Count (T-count). If the entire data payload for the OUT split
transaction is larger than 188 bytes, there will be more than one start-split transaction, each of which
require proper annotation. If host hold-offs occur, then the sequence of annotations received from the host
will not be complete, which is detected and handled by the transaction translator. See
“Split Transaction Scheduling Mechanisms for Isochronous,”
used during a sequence of start-split transactions.
The fields siTD[T-Count] and siTD[TP] are used by the host controller to drive and sequence the
transaction position annotations. It is the responsibility of system software to properly initialize these
fields in each siTD. Once the budget for a split-transaction isochronous endpoint is established, S-mask,
T-Count, and TP initialization values for all the siTD associated with the endpoint are constant. They
remain constant until the budget for the endpoint is recalculated by software and the periodic schedule
adjusted.
For IN-endpoints, the transaction translator simply annotates the response data packets with enough
information to allow the host controller to identify the last data. As with split transaction Interrupt, it is the
host controller's responsibility to detect when it has missed an opportunity to execute a complete-split. The
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Software must ensure that an isochronous split-transaction is started so that it will complete before
the end of the B-Frame.
Software must ensure that for a single full-speed isochronous endpoint, there is never a start-split
and complete-split in H-Frame, micro-frame 1. This is mandated as a rule so that case 2a and case
2b can be discriminated. According to the core USB specification, the long isochronous transaction
illustrated in Case 2b, could be scheduled so that the start-split was in micro-frame 1 of H-Frame
N and the last complete-split would need to occur in micro-frame 1 of H-Frame N+1. However, it
is impossible to discriminate between cases 2a and case 2b, which has significant impact on the
complexity of the host controller.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
for a description on how these fields are
Freescale Semiconductor
Section 21.6.12.3.1,