MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1429

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If (A .and. B .and. C .and. not(D)) then the host controller will execute a complete-split transaction. When
the host controller commits to executing the complete-split transaction, it updates QH[C-prog-mask] by
bit-ORing with cMicroFrameBit. On completion of the complete-split transaction, the host controller
records the result of the transaction in the queue head and sets QH[FrameTag] to the expected H-Frame
number. The effect to the state of the queue head and thus the state of the transfer depends on the response
by the transaction translator to the complete-split transaction. The following responses have the effects
(note that any responses that result in decrementing of the Cerr will result in the queue head being halted
by the host controller if the result of the decrement is zero):
Freescale Semiconductor
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Test D. Check to see if a start-split should be executed in this micro-frame. Note this is the same
test performed in the Do Start Split state. Whenever it evaluates to TRUE and the controller is NOT
processing in the context of a Recovery Path mode, it means a start-split should occur in this
micro-frame. Test D and Test A evaluating to TRUE at the same time is a system software error.
Behavior is undefined.
NYET (and Last). On each NYET response, the host controller checks to determine whether this
is the last complete-split for this split transaction. Last is defined in this context as the condition
where all of the scheduled complete-splits have been executed. If it is the last complete-split (with
a NYET response), then the transfer state of the queue head is not advanced (never received any
data) and this state exited. The transaction translator must have responded to all the complete-splits
with NYETs, meaning that the start-split issued by the host controller was not received. The
start-split should be retried at the next poll period.
The test for whether this is the Last complete split can be performed by XOR QH[C-mask] with
QH[C-prog-mask]. If the result is all zeros then all complete-splits have been executed. When this
condition occurs, the XactErr status bit is set and the Cerr field is decremented.
NYET (and not Last). See above description for testing for Last. The complete-split transaction
received a NYET response from the transaction translator. Do not update any transfer state (except
for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust Cerr on
this response.
-- to send a complete split in the previous micro-frame. So,
-- if the
-- 'previous bit' is set in C-mask, check C-prog-mask to
-- make sure it
-- happened.
If (previousBit bitAND QH.C-mask)then
End If
-- If the C-prog-mask already has a one in this bit position,
-- then an aliasing
-- error has occurred. It will probably get caught by the
-- FrameTag Test, but
-- at any rate it is an error condition that as detectable here
-- should not allow
-- a transaction to be executed.
If (cMicroFrameBit bitAND QH.C-prog-mask) then
rvalue = FALSE;
End if
return (rvalue)
End Algorithm
End if
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
rvalue = FALSE;
If not(previousBit bitAND QH.C-prog-mask) then
Universal Serial Bus Interfaces
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