MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1070

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
the same priority level, or if the low-priority group has only one device, the algorithm defaults to give each
device an equal number of bus grants in round-robin sequence.
For the example in
the high-priority group and three are in the low-priority group, each high-priority master is guaranteed at
least one out of three transaction slots and each low-priority master is guaranteed one out of nine
transaction slots.
In
being the current master) is 0, 2, MPC8536E, 0, 2, 1, 0, 2, 3, …, and repeating. If device 2 is not requesting
the bus, the grant sequence is 0, MPC8536E, 0, 1, 0, 3, …, and repeating. If device 2 requests the bus when
device 0 is conducting a transaction and the MPC8536E has the next grant, the MPC8536E has its grant
removed and device 2 is awarded the grant since device 2 is higher priority than the MPC8536E when
device 0 has the bus.
16.4.1.2
When no device is using or requesting the bus, the PCI arbiter grants the bus to a selected device. This is
known as parking the bus on the selected device. The selected device is required to drive the
PCI_AD[31:0], PCI_C/BE[0:3], and the PCI parity signals to a stable value, preventing these signals from
floating.
The parking mode parameter (PBACR[PM]) determines which device the arbiter selects for parking the
PCI bus. If PBACR[PM] = 0 (or if the bus is not idle), then the bus is parked on the last master to use the
bus. If the bus is idle and PBACR[PM] = 1, the bus is parked on the PCI controller.
16.4.1.3
The PCI bus arbiter has a feature that allows it to lock out any masters that are broken or ill-behaved. The
broken master feature is controlled by programming bit 12 of the PCI bus arbitration control register (0 =
enabled, 1 = disabled).
When the broken master feature is enabled, a granted device that does not assert PCI_FRAME within 16
PCI clock cycles after the bus is idle, has its grant removed and subsequent requests are ignored until its
16-44
Figure
16-48, the grant sequence (with all devices, except device 4 requesting the bus and device 3
PCI Bus Parking
Broken Master Lock-Out
Device 0
Figure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(1/3)
High-Priority Group
16-48, assume that several devices are requesting the bus. If two masters are in
Device 2
(1/3)
Figure 16-48. PCI Arbitration Example
Priority
Low-
(1/3)
Slot
PQIII
(1/9)
Low-Priority Group
Device 1
(1/9)
Device 3
(1/9)
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