MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 945

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.6.7.4.1
The eTSEC receive filer has been enhanced with the addition of a general-purpose event bit. This event
bit can be used in conjunction with filing table rules to identify 1588 packets and indicate these packets by
setting special timer status register bits (TMR_STAT). Additionally, 1588 packets can be easily identified
by upper-layer software by using the filer to queue all PTP packets to one or more predefined virtual
queues. See
14.6.7.5
Software has the option to write the time stamp of the transmitted frame to memory in the padding
alignment bytes (PAL) located between the TxFCB and the frame data. It is required that a minimum of
two TxBDs are used. The first points to the start of the 8 byte TxFCB. The second points to the start of
frame data. In memory, the TxFCB, and at least the first 16 bytes of the TxPAL must be adjacent, i.e.,
located in continguous memory locations, as depicted in
The first TxBD[TOE] bit is set. When the TMR_CTRL[Record Time-stamp In PAL Enable] and
TxFCB[PTP] bits are set, the timestamp is written to memory location TxBD[Data Buffer Pointer]+16.
The second TxBD’s Data Length must either contain the full frame length, or a value greater than the
TxThreshold setting. Refer to
TMR_TXTSn_H/L and TMR_TXTSn_ID registers still function normally.
14.6.7.5.1
The TxPAL is updated with a time-stamp before closing the second TxBD. The TxBD[I] bit can be set for
the second TxBD frame to cause an interrupt (via IEVENT[TXF]) after the time-stamp has been written
to the TxPAL.
When time-stamps are inserted into the TxPAL, the TMR_TXTSn_H/L and TMR_TXTSn_ID registers
still function normally. Therefore, the 1588 interrupt can be triggered by using the TMR_PEVENT register
bits TXP1, and TXP2.
Freescale Semiconductor
Preamble
Section 14.6.5.2.1, “Filing Rules
Time-Stamp Insertion on Transmit Packets
General Purpose Filer Rule
Interrupts
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-167. Time-Stamp Insertion Programming Requirements
TMR_CTRL[RTPE]=1
10101011
SFD
Requirement
Time Stamp Point
Table
SRC
Figure 14-151. PTP Packet Format
14-167. When time-stamps are inserted into the TxPAL, the
DEST
for further information.
L/T
IP_H
Figure
UDP_H
If TMR_CTRL[RTPE]=0, then no time-stamp is
14-152.
Behavior if requirement is not met
Enhanced Three-Speed Ethernet Controllers
Data
written to a TxPAL.
PTP_Message
CRC
14-197