MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1601

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.3.2.4
The trace buffer transaction mask register (TBTMR) shown in
types to monitor. Each bit in the TBTMR represents a transaction type on the selected interface. The
transaction associated with any particular bit depends on the interface being monitored as specified by
TBCR1[IFSEL]. Note that the transactions used for defining trace buffer events are the same as those
defined for watchpoint monitor events. Thus,
each interface. Setting a bit enables a hit when this transaction is matched (provided all other match criteria
are met and TBCR0[TMD] is clear).
Different interfaces support different transaction types, and the same bit may represent different
transaction types depending on the interface.
Table 25-18
25.3.2.5
The trace buffer status register (TBSR) shown in
buffer.
Freescale Semiconductor
Offset 0x058
Reset
0–31
Bits
Offset 0x05C
Reset
W
R
W
R
0
Name
TBTM Trace buffer transaction mask. Each bit corresponds to a transaction type as defined in
ACT TRIG STP WRAP
0
describes the TBTMR field.
Trace Buffer Transaction Mask Register (TBTMR)
Trace Buffer Status Register (TBSR)
1
transaction associated with a bit depends on the interface being monitored. A value of 1 for a given mask bit
enables the matching of the transaction associated with that bit. These bits are meaningful only when
TBCR0[TMD]=0.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
Figure 25-12. Trace Buffer Transaction Mask Register (TBTMR)
3
Figure 25-13. Trace Buffer Status Register (TBSR)
4
Table 25-18. TBTMR Field Descriptions
Table 25-12
Figure 25-13
All zeros
All zeros
TBTM
—
Description
defines the transaction types associated with
Figure 25-12
indicates the operational state of the trace
Debug Features and Watchpoint Facility
specifies which transaction
23 24
Access: Read/Write
C_INDX
Table
Access: Read/Write
25-12. The
31
25-19
31