MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1669

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.6.44, 14-109
14.5.3.6.45, 14-110
14.5.3.9.2, 14-119
14.5.3.10.2, 14-121
14.5.3.11.1, 14-123
14.5.3.11.9, 14-129
14.5.3.11.12, 14-131
14.5.3.11.13, 14-132
14.6.3.9, 14-171
14.6.5.3.1, 14-190
14.6.7, 14-194
Freescale Semiconductor
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Corrected access designation for CAR1 and CAR2 registers to be ‘w1c’
Replaced ATTRELI[EI] field description with the following:
Extracted index. Points to the first byte, as a multiple of 64 bytes, within the
receive frame as sent to memory from which to begin extracting data.
Corrected RFBPTR0–RFBPTR7 register offset designation to read as follows:
Replaced TMR_CTRL[CIPH] field description with the following:
Oscillator input clock phase.
0
1
Changed access of register TMR_ACC from read only to read/write.
Changed access of register TMR_ALARM1–2_H/L from mixed to read/write
Changed access of register TMR_FIPER1–3 from mixed to read/write
Replaced second sentence of third paragraph (began “Since the pause timer
commences counting...”) with the following:
The controller completes any frame in progress before stopping transmission and
does not commence counting the pause time until transmit is idle.
Replaced entire section, “Priority-Based Queuing (PBQ),” with the following:
PBQ is the simplest scheduler decision policy. The enabled TxBD rings are
assigned a priority value based on their index. Rings with a lower index have
precedence over rings with higher indices, with priority assessed on a
frame-by-frame basis. For example, frames in TxBD ring 0 have higher priority
than frames in TxBD ring 1, and frames in TxBD ring 1 have higher priority than
frames in TxBD ring 2, and so on.
The scheduling decision is then achieved as follows:
Added the following note after third paragraph of this section:
IEEE 1588 timestamping is not supported in conjunction with the SGMII 10/100
interface mode.“
eTSEC1:0x2_4C44+8 n ; eTSEC2:0x2_5C44+8 n ;
eTSEC3:0x2_6C44+8 n ; eTSEC4:0x2_7C44+8 n ”
loop
endloop
# start or S/W clear of TSATn
ring = 0;
while ring <= 7 loop
endloop
non-inverted timer input clock
inverted timer input clock (NOTE: this setting is reserved if CKSEL=01.)
if enabled(ring) and not ring_empty(ring) then
else
endif
transmit_frame(ring);
ring = 0;
ring = ring + 1;
Revision History
B-5