MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1390

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.5.5.4
The last five DWords of a queue element transfer descriptor make up an array of physical memory address
pointers. These pointers reference the individual pages of a data buffer.
System software initializes the Current Offset field to the starting offset into the current page, where
current page is selected with the value in the C_Page field.
21.5.6
Figure 21-40
1
2
3
21-56
dt
31–12
31
11–0
Mult
Bits
Offsets 0x04 through 0x0B contain the static endpoint state.
Host controller read/write; all others read-only.
Offsets 0x10 through 0x2F contain the transfer overlay.
1
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RL
Current Offset
Buffer Pointer
(Pages 1–4)
Port Number
(Page 0)/
(page n )
Queue Head
Name
C
qTD Buffer Page Pointer List
shows the queue head structure.
—
Total Bytes to Transfer
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Maximum Packet Length
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Each element in the list is a 4K page aligned physical memory address. The lower 12 bits in each
pointer are reserved (except for the first one), as each memory pointer must reference the start of
a 4K page. The field C_Page specifies the current active pointer. When the transfer element
descriptor is fetched, the starting buffer address is selected using C_Page (similar to an array index
to select an array element). If a transaction spans a 4K buffer boundary, the host controller must
detect the page-span boundary in the data stream, increment C_Page and advance to the next
buffer pointer in the list, and conclude the transaction via the new buffer pointer.
Reserved in all pointers except the first one (that is, Page 0). The host controller should ignore all
reserved bits. For the page 0 current offset interpretation, this field is the byte offset into the current
page (as selected by C_Page). The host controller is not required to write this field back when the
qTD is retired. Software should ensure the reserved fields are initialized to zeros.
Queue Head Horizontal Link Pointer
Alternate Next qTD Pointer
Hub Addr
Current qTD Pointer
2
Next qTD Pointer
Figure 21-40. Queue Head Layout
Table 21-54. qTD Buffer Pointer
2
2
2
2
2
ioc
15
H
2
2
2
dtc EPS
14
C_Page
µFrame C-mask
2
13 12 11 10
2
Cerr
Description
EndPt
2
0000
Code
9
PID
S-bytes
8
2
0000_0000_0000
0000_0000_0000
Current Offset
7
I
2
6
µFrame S-mask
5
C-prog-mask
Device Address
4
Status
00
2
NakCnt
Freescale Semiconductor
3
0000
00000
2
FrameTag
2
Typ
2
2
1
T
T
T
0
2
2
2
0x1C
0x14
0x18
0x20
0x24
0x2C
0x04
0x08
0x10
0x28
0x0C
Offset
0x00
3,4
3,4
3,4
3,4
3,4
1
1
3
3
3