MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1675

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C.3.3.2
Table C-5
possible for the
C.4
Unless specifically mentioned in the following sections, all peripheral blocks in the MPC8535E are
identical to those of the MPC8536E.
C.4.1
The MPC8535E supports two PCI Express interfaces, PCI Express 2 and PCI Express 3, with maximum
width of 4 bits. One of the configurations in
in
C.4.2
The MPC8535E supports two fully functional USB controllers, USB1 and USB2, that are compatible with
USB specification revision 2.0.
Freescale Semiconductor
TSEC1_TXD2,
TSEC3_TXD2,
PULSE_OUT1
TSEC_1588_
Default (111)
Section C.3.3.1, “SerDes1 (PCI Express) I/O Port
Functional
Signal
Differences in Peripheral Blocks
shows the configuration of I/O ports and bit rates (and required reference clocks) that are
PCI Express Interfaces
USB Controllers
SerDes2 (SATA) I/O Port Selection
Reset Configuration
cfg_srds2_prtcl[0:2]
SerDes2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Table C-6. Supported SerDes 1 (PCI Express) Configurations
interfaces.
Table C-5. SerDes2 I/O Port Selection (MPC8535E)
4/E
(Binary)
Value
000
001
010
011
100
101
110
111
PEX2 x2
PCI Express Signal/Lane
Table C-6
Reserved
Reserved
Reserved
SATA1
eTSEC1 Ethernet interface uses parallel interface according to POR
config input cfg_tsec1_prtcl.
Reserved
Reserved
SATA1 disabled.
eTSEC1 SGMII (1.25 Gbps) -> Serdes2 Lane A (POR config input
cfg_tsec1_prtcl should be left in its default setting).
SATA1 disabled.
eTSEC1 Ethernet interface uses parallel interface according to POR
config input cfg_tsec1_prtcl.
Serdes2 disabled (default)
5/F
PEX2 x4
SerDes2 Lane A.
Selection.”
can be selected during power-on reset as described
6/G
PEX3 x2
7/H
Meaning
MPC8535E
C-5