MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 480

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
bit is successfully cleared and no other interrupt conditions are present, the controller negates its interrupt
signal. If any interrupts are still pending in the ISR, the interrupt remains asserted.
10.5.4
The controller registers are described in detail in the following sections.
10.5.4.1
The EUASR indicates which EUs are reserved by a particular channel. When an EU is already assigned,
it is inaccessible to any other channel.
The EAUSR fields are displayed in
indicates the EU’s assigned channel. The field values and corresponding channel assignments are shown
in
10.5.4.2
The SEC controller generates the interrupt outputs from all possible interrupt sources. These outputs are
enabled, displayed, and cleared by the IER, ISR, and ICR, respectively. These three registers share a
10-50
Offset 0x3_1028
Reset 1
Reset 1
Table
W
W
R
R
32
0
10-18.
1
1
—
—
Controller Registers
1
1
EU Assignment Status Register (EUASR)
Interrupt Enable, Interrupt Status, and Interrupt Clear Registers (IER,
ISR, ICR)
1
1
3
0
1
4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
AFEU
0
1
—
0
1
Figure 10-16. EU Assignment Status Register (EUASR)
7
0
1
1
0
8
Table 10-18. Channel Assignment Value
CRCU
1
0
—
Figure
0xA–0xE
1
0
Value
0x0
0x1
0x2
0x3
0x4
0xF
11 12
1
0
10-16. The register has a four-bit field for each EU which
0
0
MDEU
0
0
—
0
0
No channel assigned
Channel 1
Channel 2
Channel 3
Channel 4
Undefined
Unavailable
15 16
47 48
0
0
1
1
Channel
1
1
—
—
1
1
19 20
51 52
1
1
0
0
AESU
PKEU
0
0
0
0
23 24
55 56
0
0
1
1
Freescale Semiconductor
1
1
—
—
1
1
Access: Read only
27 28
59 60
1
1
0
0
0
RNG
0
DEU
0
0
31
63
0
0