MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1419

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.6.12.1.1 Asynchronous—Do-Start-Split
Do-Start-Split is the state which software must initialize a full- or low-speed asynchronous queue head.
This state is entered from the Do-Complete-Split state only after a complete-split transaction receives a
valid response from the transaction translator that is not a Nyet handshake.
For queue heads in this state, the host controller executes a start-split transaction to the transaction
translator. If the bus transaction completes without an error and PID Code indicates an IN or OUT
transaction, then the host controller reloads the error counter (Cerr). If it is a successful bus transaction and
the PID Code indicates a SETUP, the host controller will not reload the error counter. If the transaction
translator responds with a Nak, the queue head is left in this state, and the host controller proceeds to the
next queue head in the asynchronous schedule.
If the host controller times out the transaction (no response, or bad response) the host controller decrements
Cerr and proceeds to the next queue head in the asynchronous schedule.
21.6.12.1.2 Asynchronous—Do-Complete-Split
This state is entered from the Do-Start-Split state only after a start-split transaction receives an Ack
handshake from the transaction translator.
For queue heads in this state, the host controller executes a complete-split transaction to the transaction
translator. If the transaction translator responds with a Nyet handshake, the queue head is left in this state,
the error counter is reset and the host controller proceeds to the next queue head in the asynchronous
schedule. When a Nyet handshake is received for a bus transaction where the queue head's PID Code
indicates an IN or OUT, the host controller reloads the error counter (Cerr). When a Nyet handshake is
received for a complete-split bus transaction where the queue head's PID Code indicates a SETUP, the host
controller must not adjust the value of Cerr.
Independent of PID Code, the following responses have the indicated effects:
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Transaction Error (XactErr). Timeout/data CRC failure. The error counter (Cerr) is decremented
by one and the complete split transaction is immediately retried (if possible). If there is not enough
time in the micro-frame to execute the retry, the host controller ensures that the next time the host
controller begins executing from the Asynchronous schedule, it must begin executing from this
queue head. If another start-split (for some other endpoint) is sent to the transaction translator
before the complete-split is really completed, the transaction translator could dump the results
(which were never delivered to the host). This is why the core specification states the retries must
be immediate. When the host controller returns to the asynchronous schedule in the next
micro-frame, the first transaction from the schedule will be the retry for this endpoint. If Cerr went
to zero, the host controller halts the queue.
NAK. The target endpoint Nak’d the full- or low-speed transaction. The state of the transfer is not
advanced and the state is exited. If the PID Code is a SETUP, then the Nak response is a protocol
error. The XactErr status bit is set and the Cerr field is decremented.
STALL. The target endpoint responded with a STALL handshake. The host controller sets the halt
bit in the status byte, retires the qTD but does not attempt to advance the queue.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Universal Serial Bus Interfaces
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