MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 665

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3.1.5
The refresh timer prescaler register (MRTPR), shown in
provide the UPM refresh timers clock.
Table 13-12
13.3.1.6
The memory data register (MDR), shown in
from the RAM array for UPM read or write commands. MDR also contains data written to or read from
an external NAND Flash EEPROM for FCM write address, write data, and read status commands. MDR
Freescale Semiconductor
18–21
22–25
26–31
Offset 0x0_5084
Reset
8–31
Bits
Bits
0–7
W
R
0
Name
Name
MAD
WLF
PTP
TLF
—
describes MRTPR fields.
Memory Refresh Timer Prescaler Register (MRTPR)
UPM/FCM Data Register (MDR)
Write loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat write pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Refresh loop field. Determines the number of times a loop defined in the UPM n will be executed for a refresh
service pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Machine address. RAM address pointer for the command executed. This field is incremented by 1, each time
the UPM is accessed and the OP field is set to WRITE or READ. Address range is 64 words per UPM n .
Refresh timers prescaler. Determines the period of the refresh timers input clock. The system clock is divided
by PTP except when the value is 00000_0000, which represents the maximum divider of 256.
Reserved
PTP
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 13-8. Memory Refresh Timer Prescaler Register (MRTPR)
Table 13-11. M x MR Field Descriptions (continued)
7
8
Table 13-12. MRTPR Field Descriptions
Figure 13-9
All zeros
Description
Description
Figure
and
Figure
13-8, is used to divide the system clock to
—
13-10, contains data written to or read
Enhanced Local Bus Controller
Access: Read/Write
13-23
31