MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1263

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

in length. The length transmitted by the SATA IP is determined by the PIO setup FIS that is sent by the
device requesting the ATAPI command.
19.3.7.5
This is a software constructed table of addresses to use to complete the data transfer. Up to 16 structures
can be supported in the current command descriptor. The format of the address entry is defined by the
“Block vector structures for passing segmented data type of the IEEE Std. 1212.1-1993”. The total
definable length supported in the 16 entries is 64 Mbytes.
Table 19-31
Table 19-32
19.3.8
As part of the host self-diagnostic operation, a vendor-specific BIST mode is supported. This mode, in
conjunction with a PHY that supports serial loopback, allows for the test of the SATA controller operation.
The mode exercises the following paths:
Freescale Semiconductor
31–2
1–0
Bit
30–23
21–2
•
•
•
•
•
•
1–0
Bit
31
22
DMA controller FIS transmission
Command layer FIS transmission
Transport layer Tx FIFO FIS transmission
Link layer FIS transmission
PHY modes
Link layer FIS reception
Name
DBA
—
Vendor-Specific BIST Operation
shows word 0—data base address—of the PRDT.
shows word 3—description information—of the PRDT.
Physical Region Descriptor Table (PRDT)
Name
DDC
EXT
Data base address. Indicates the 32-bit physical address of the data block. The block must be word aligned,
indicated by bits 1–0 being “reserved, must be 00.”
Reserved
—
—
C
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
If the extension flag is set to 1, then the DBA field contains the address of the extension segment,
and the DWC field contains the size of this extension segment (this is called an “indirect descriptor”).
Reserved
Data snoop enable bit. When this bit is set, all data read/write operations associated with the PRD
entry for this command will be snoopable.
Data word count. A 0-based value that Indicates the length, in words, of the data block. A maximum
length of 4 Mbytes may exist for any entry. Bits 1–0 of this field must always be 0 to indicate that size
is in words. A value of 0x0_0000 indicates a full 4 Mbytes transfer.
Reserved
Table 19-32. Word 3—Description Information
Table 19-31. Word 0—Data Base Address
Description
Description
SATA Controller
19-33