MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 873

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-115
14.5.3.11.3 Timer Event Mask Register (TMR_TEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_TEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset. Figure 14-116 describes
the definition for the TMR_TEMASK register.
Freescale Semiconductor
16–23
27–31
8–13
Bits
0–6
14
15
24
25
26
6
7
Name
ALM2
ALM1
ETS2
ETS1
PP1
PP2
PP3
describes the fields of the TMR_TEVENT register fields for the timer.
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—
—
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
External trigger 2 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
External trigger 1 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
Reserved
Current time equaled alarm time register 2
0 alarm time has not be reached yet
1 alarm time has been reached
Current time equaled alarm time register 1
0 alarm time has not be reached yet
1 alarm time has been reached
Reserved
Indicates that a periodic pulse has been generated based on FIPER1 register.
0 periodic pulse not generated
1 periodic pulse generated
Indicates that a periodic pulse has been generated based on FIPER2 register.
0 periodic pulse not generated
1 periodic pulse generated
Indicates that a periodic pulse has been generated based on FIPER3 register.
0 periodic pulse not generated
1 periodic pulse generated
Reserved
Table 14-115. TMR_TEVENT Register Field Descriptions
Description
Enhanced Three-Speed Ethernet Controllers
14-125