MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1571

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Nothing
System cycles
Cycles a read is returning data from
DRAM
Cycles a write transfers data to DRAM
Pipelined read misses in the row open
table
Pipelined read or write misses in the row
open table
Non-pipelined read misses in the row
open table
Non-pipelined read or write misses in the
row open table
Pipelined read hits in the row open table
Pipelined read or write hits in the row
open table
Non-pipelined read hits in the row open
table
Non-pipelined read or write hits in the
row open table
Forced page closings not caused by a
refresh
Row open table misses
Row open table hits
Force page closings
Read-modify-write transactions due to
ECC
Forced page closings due to collision
with bank and sub-bank
Reads or writes from core (data and inst)
Freescale Semiconductor
Event Counted
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events
C:64 and Ref:20
Number
DDR Memory Controller Events
C1:121
C3:124
C5:120
C7:121
Ref:19
Ref:11
Ref:12
Ref:13
C2:64
C4:64
C6:64
C8:64
C1:64
C2:65
C3:64
C4:65
C5:64
Ref:0
General Events
Register counter holds current value
CCB (platform) clock cycles
Each data beat returned to the memory controller on the DRAM
interface
Each data beat transferred to the DRAM
Row open table read misses issued while a read is outstanding
Row open table read or write misses issued while a read or write is
outstanding
Row open table read misses issued when no reads are outstanding
Row open table read or write misses issued when no reads or writes
are outstanding
Row open table read hits issued when a read is outstanding
Row open table read or write hits issued when a read or write is
outstanding
Row open table read hits issued when no reads are outstanding
Row open table read or write hits issued when no reads or writes are
outstanding
Precharges issued to the DRAM for any reason except refresh. The
possibilities are as follows:
Transactions that miss in the row open table
Transaction that hit in the row open table
Forced page closings including those due to refreshes
If ECC is enabled and a transaction requires byte enables, a
read-modify-write sequence is issued on the DRAM interface.
Increments if a new transaction must be issued to an active bank
and sub-bank that has a different row open
—
• A new transaction must be issued to an already active bank and
• A new transaction must be issued, but the row open table is full
• The BSTOPRE interval expired for an open row.
sub-bank that has a different row open.
and there is no bank/sub-bank match between the current
transaction and the row open table.
Description of Event Counted
Device Performance Monitor
24-17