MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1481

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9.5.1
Given that the optional PCI configuration registers are not included in this implementation, there is no
corresponding bit level timing adjustments like those provided by the Frame Adjust register in the PCI
configuration registers. Starts of microframes are timed precisely to 125 µsec using the transceiver clock
as a reference clock. That is, 60 MHz transceiver clock for 8-bit physical interfaces and full-speed serial
interfaces or 30 MHz transceiver clock for 16-bit physical interfaces.
21.9.6
21.9.6.1
The modules support multiple physical interfaces which can operate in different modes when the module
is configured with the software programmable Physical Interface Modes. The control bits for selecting the
PHY operating mode have been added to the PORTSC register providing a capability that is not defined
by the EHCI specification.
21.9.6.2
21.9.6.2.1
The port connect methods specified by EHCI require setting the port reset bit in the register for a duration
of 10 msec. Due to the complexity required to support the attachment of devices that are not high speed
there are counter already present in the design that can count the 10 msec reset pulse to alleviate the
requirement of the software to measure this duration. Therefore, the basic connection is then summarized
as the following:
21.9.6.2.2
After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port
speed. Unlike the EHCI implementation which will re-assign the port owner for any device that does not
connect at High-Speed, this host controller supports direct attach of non-HS devices. Therefore, the
following differences are important regarding port speed detection:
Freescale Semiconductor
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[Port Change Interrupt] Port connect change occurs to notify the host controller driver that a device
has attached.
Software shall write a ‘1’ to the reset the device.
Software shall write a ‘0’ to the reset the device after 10 msec.
— This step, which is necessary in a standard EHCI design, may be omitted with this
[Port Change Interrupt] Port enable change occurs to notify the host controller that the device in
now operational and at this point the port speed has been determined.
Port owner is read-only and always reads 0.
implementation. Should the EHCI host controller driver attempt to write a ‘0’ to the reset bit
while a reset is in progress the write will simple be ignored and the reset will continue until
completion.
Miscellaneous Variations from EHCI
Frame Adjust Register
Programmable Physical Interface Behavior
Discovery
Port Reset
Port Speed Detection
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Universal Serial Bus Interfaces
21-147