MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1494

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.3
The following subsections provide information about signals that serve as global utilities.
23.3.1
Table 23-1
23.3.2
Table 23-2
23-2
CKSTP_IN
ASLEEP
Signal
External Signal Description
Signal Name
CKSTP_OUT
summarizes the external signals used by the global utilities block.
describes signals in the global utilities block in detail.
POWER_EN
POWER_OK
Signals Overview
Detailed Signal Descriptions
CKSTP_IN
CLK_OUT
ASLEEP
I/O
O
I
Asleep. See
device completes its power-on reset sequence and reaches its ready state.
Checkstop in
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Meaning
Meaning
Timing Assertion—May occur at any time; may be asserted asynchronously to the input clocks.
Timing Assertion—May occur at any time; may be asserted asynchronously to the input clocks.
State
State
I/O
O
O
O
O
I
I
Asserted—Indicates that the device is either still in its power-on reset sequence or it has
Negated—The device is not in sleep mode. (It has either awakened from a power-down state,
Negation—Negates synchronously with SYSCLK when leaving power-on sequence;
Asserted—Indicates that the e500 core must enter a hard stop condition. All e500 clocks are
Negated—Indicates that normal operation should proceed.
Negation—Must remain asserted until the MPC8536E is reset with assertion of HRESET.
Section 23.5.1.6.3, “Sleep
Signals that the device has reached a sleep state.
Checkstop input
Checkstop output.
Clock out. Selected by CLKOCR values.
Indication to turn the power on and off.
Indication that the power has returned to specified
level after a wakeup event occurs.
Table 23-2. Detailed Signal Descriptions
reached a sleep state after a power-down command is issued by software.
or has completed the POR sequence.)
otherwise negation is asynchronous.
turned off. CKSTP_OUT is asserted. The rest of MPC8536E device logic, including
memory controllers, internal memories and registers, and I/O interfaces, remains
functional.
Table 23-1. External Signal Summary
Description
Mode.” After negation of HRESET, ASLEEP is asserted until the
Description
Reference (Section/page)
Table 23-2 on page 23-2
Table 23-2 on page 23-2
23.5.1.16.2/23-61
23.5.1.16.1/23-60
23.5.1.6.3/23-50
23.4.1.25/23-33
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