MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 171

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4
Reset, Clocking, and Initialization
This chapter describes the reset, clocking, and some overall initialization of the MPC8536E, including a
definition of the reset configuration signals and the options they select. Additionally, the configuration,
control, and status registers are described. Note that other chapters in this book may describe specific
aspects of initialization for individual blocks.
4.1
The reset, clocking, and control signals provide many options for device operation. Additionally, many
modes are selected with reset configuration signals during a hard reset (assertion of HRESET).
4.2
Table 4-1
signal descriptions, but
The following sections describe the reset and clock signals in detail.
Freescale Semiconductor
SD2_REF_CLK/
SD2_REF_CLK
HRESET_REQ
SD_REF_CLK/
SD_REF_CLK
DDRCLK
HRESET
SRESET
SYSCLK
READY
Signal
RTC
Overview
External Signal Descriptions
summarizes the external signals described in this chapter.
I/O
O Hard reset request output. An internal block requests that HRESET be asserted.
O The MPC8536E has completed the reset operation and is not in a power-down
I
I
I
I
I
I
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Hard reset input. Causes a power-on reset (POR) sequence.
Soft reset input. Causes mcp assertion to the core
(nap, doze or sleep) or debug state.
Primary clock input to the MPC8536E
Clock input to the MPC8536E that sources the DDR controller complex PLL
Real time clock input
SERDES high-speed interface reference clock
Second SERDES high-speed interface reference clock
Table 4-1
contains references to additional sections that contain more information.
Table 4-1. Signal Summary
Description
Table 4-2
and
Table 4-3
(Section/Page)
have detailed
References
4.4.4.1/4-24
4.4.4.1/4-24
4.4.4.4/4-26
4.4.4.2/4-25
4.4.4.2/4-25
4.4.1.2/4-8
4.4.1.1/4-8
4.4.2/4-9
—
4-1