MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 337

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 8.5.12, “Error Management,”
Freescale Semiconductor
1. All signals are connected in common (in parallel) except for MCS[0:3], MCK[0:5], MDM[0:8], and the data bus signals.
2. Each of the MCS[0:3] signals correspond with a separate physical bank of memory.
3. Buffering may be needed if large memory arrays are used.
4. MCK[0:5] may be apportioned among all memory devices. Complementary bus is not shown.
DDR
Controller
MDQS[0:8]
MDQ[0:63]
MECC[0:7]
MDM[0:8]
MCK[0:5]
MCK[0:5]
MBA[2:0]
MCS[0:3]
MA[15:0]
MRAS
MCAS
MCKE
MWE
Figure 8-48. Example 256-Mbyte DDR SDRAM Configuration With ECC
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MCS0
0
1
2
3
4
5
6
7
8
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
8M
8M
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
8 SDRAM
8 SDRAM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
2 Mx8 SDRAM
DQ[0-7]
DQ[7:0]
DQ[7:0]
Bank 0
8M
MDQS
DQ(7-0)
MDQS
DQ(7-0)
DQ[0-7]
DQ[0-7]
To all SDRAM
Devices in
Common
DQ[0-7]
explains how the DDR memory controller handles errors.
DQ[0-7]
72 (64 Mbytes)
Memory Data Bus and Strobes
MDQS[8]
MDQS[0]
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQ[32:39]
MDQ[40:47]
MDQ[48:55]
MDQ[56:63]
ECC[0:7]
MDQS[7]
MCS1
0
1
2
3
4
5
6
7
8
A[11:0]
BA[1:0]
RAS
CAS
WE
CKE
CK
CS
DM
A[11:0]
BA[1:0]
RAS
CAS
CKE
CK
CS
DM
WE
8M
8M
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A(11-0)
BA(1-0)
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2Mx8 SDRAM
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
8 SDRAM
2Mx8 SDRAM
8 SDRAM
Bank 1
8M
A[0-11]
BA[0-1]
RAS
CAS
CKE
CLK
CS
DM
2 Mx8 SDRAM
2Mx8 SDRAM
DQ[0-7]
DQ[7:0]
DQ[7:0]
DQ(7-0)
MDQS
MDQS
DQ(7-0)
DQ[0-7]
DQ[0-7]
72 (64 Mbytes)
DQ[0-7]
DQ[0-7]
MDQS[8]
MDQS[0]
MDQ[0:7]
MDQ[8:15]
MDQ[16:23]
MDQ[24:31]
MDQ[32:39]
MDQ[40:47]
MDQ[48:55]
MDQ[56:31]
ECC[0:7]
MDQS[7]
DDR Memory Controller
Banks 2–3
8-63