MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1569

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PMLCAn[BGRAN] specifies the maximum number of cycles between individual events for them to
qualify as members of the same burst sequence.
The burstiness distance field (PMLCAn[BDIST]) and threshold/burstiness multiplier field
(PMLCBn[TBMULT]) specify the acceptable number of cycles between the end of a burst sequence and
the beginning of a new sequence for a group of event occurrences to be counted as an individual burst. The
product of the burstiness distance field and the threshold/burstiness multiplier field determine the
burstiness distance value used to determine when another burst sequence can begin. Note that the burst
distance count begins when a new burst sequence ends and the PMC is incremented. No new burst
sequence may begin until the burst distance count has reached zero. After the burst distance count reaches
zero, it holds the zero value indicating that a new burst sequence can be counted. The burst distance count
begins again when a new burst sequence is identified and counted.
Burstiness counting is disabled when the definition of a burst is ambiguous, that is, when the burst size
field is less than two, or the burst distance is zero. When burstiness counting is disabled, regular counting
is allowed.
Figure 24-10
burst sequence may not begin until the burst distance count expires.
Three internal counters track the different values required for burstiness counting.
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Burstiness size is monitored by a counter. It is loaded with the value specified in the local control
register when the burst granularity counter and the burst distance counters reach zero, and no new
event is occurring. It always decrements when the following conditions occur: its value is not
already zero, an event occurs, and the burst distance count equals zero.
Burstiness granularity is monitored by a counter that is loaded with the specified value in the local
control register on the rising edge of an event occurrence whenever the burst distance count equals
zero. The granularity counter is decremented (if it has not already reached zero) when an event is
not occurring and burst distance count equals zero.
Burstiness distance is measured by a counter that is loaded with the product of PMLCBn[BDIST]
and PMLCBn[TBMULT] when a burst sequence has been identified and counted. This counter is
decremented when burstiness counting is enabled (and the counter has not already reached zero).
shows that the burst distance is measured from the end of one burst sequence and that a new
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Device Performance Monitor
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