MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 209

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Config Address structure is shown in
Freescale Semiconductor
CNT = 0
CNT = 1 EC DLY CF
0–29
Bits
3–29
30
31
Bits
30
31
0
1
2
Address Address bits 0–29. The data in the Config Data field is copied by the e500 core to this address. The two
Name
CNT
Name
CNT
0
DLY
—
EC
CF
—
—
1
least significant bits of the address (30:31) are always considered to be zero, as are the upper 4 bits of
the 36-bit address.
Reserved. Must be zero.
Control. Select between Address mode and Control mode.
0 Address mode
1 Control mode
End Configuration. Indicates the end of the configuration stage. Valid only if bit CNT is set.
0 Not the last Config Address field.
1 The Last Config Address field. The e500 core will stop the configuration stage and start to copy the
This must be set for Config Address Word N, and not be set for Config Address words prior to Config
Delay. Instruct the e500 core to perform delay according to the number that is specified in the adjacent
Config Data field. The adjacent Config Data field provides the delay measured in terms of the number of
8 CCB clocks. Valid only if bit CNT is set.
0 No delay.
1 Delay.
Change frequency. Instruct the e500 core to perform sequence of operations to setup the eSPI CS1 mode
register with the frequency related (PM and DIV16) bits as defined by the user. The adjacent Config Data
field will be written to the eSPI mode register. Software will use DIV16 and PM bits and mask all other bits
such that they will not change. Software will perform the necessary steps which are required by the eSPI
controller before and after changing the eSPI mode register.
This only takes effect after all of the Configuration and Control words have been read.
Reserved. Must be zero.
Reserved. Must be zero.
Control. Select between Address mode and Control mode.
(0 Address mode)
1
Note: When CNT=1, bits 0–29 select the control instruction. Only one bit in the range of bits 0–29 can be
2
user’s code.
Address Word N.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Control mode
set at any specific control instruction. A control instruction with bits 0–29 all cleared is also illegal.
3
Table 4-39. Config Address Field Description, CNT = 0
Table 4-40. Config Address Field Description, CNT = 1
Figure 4-12. Config Address Fields
Figure
Address
4-12.
Description
Description
—
Reset, Clocking, and Initialization
29 30
— CNT
— CNT
31
4-39